Daniele Pinto wrote: Hello, I downloaded alliance 3.2 for linux. I write circuit in VHDL language. How can I include library in my behavioral description? For example: ieee std_logic_1164 ieee std_logic_arith How can I use my VHDL library? No way... Alliance only supports a VHDL subset with predefine types. See "man vhdl" Is there a waver to wiev wave form after simulation? yes : xpat -- Sincerely, Olivier. ==================================================================== Olivier SIROL Alliance Team ASIM/LIP6/UPMC Coul. 55-65, 2e etg, Bur. 213 75252 Paris Cedex 05 mailto:Olivier.Sirol@lip6.fr Tel: (33/0) 1.44.27.74.78 http://asim.lip6.fr/~czo/ Fax: (33/0) 1.44.27.72.80