I was unable to compile with (asimut -b -c) a simple VHDL specification of an entity with a process in its architecture. It looked like this: entity clk_gen is port(clock : out bit); end clk_gen; architecture clk_gen_arch of clk_gen is begin clk:process -- clock generator begin clock <= '0'; wait for 5 ns; clock <= '1'; wait for 5 ns; end process; end clk_gen_arch; The asimut returned errors on most lines begining with the one in witch process is declared and wrote "illegal concurrent statement". What am I doing wrong? Or is it some other problem that I don't know about. Nick