These projects range from medium complexity ASICs developed in 6 months by a couple of designers Data-safe, TNT, Smal, Rf264,etc...) to high complexity circuits (FRISC, Multick, StaCS, Rapid2, Rcube) developed by a team of PhD students.
The three largest circuits described in table 7 use not only standard-cells but also parameterized generators for regular blocks like RAMs, data-paths, or floating-point operators. The FRISC and TNT projects successfully used the Cadence and Compass place and route tools, and therefore prove the interoperability of the Alliance system.
A picture of the StaCS processor is shown figure 8.