alliance-support '01
warning from scmap


marla (marla@asti.dost.gov.ph)
Tue, 19 Jun 2001 09:41:38 +0800

Hi! I am following your tutorial on the 1-bit fulladder. I’m now on the stage of synthesizing the logic so I used scmap. The following was generated: bash-2.02$ scmap halfadder halfadder1 @@@@ @ @@@@ @ @ @@ @@ @@ @@ @ @@ @ @@@ @@ @ @@@ @@ @@@ @@@@ @@@ @@@ @@@@ @@ @@@ @@ @@ @@ @ @@@ @@ @@@@ @@ @@ @@ @@ @@ @@ @@ @@ @@@ @@ @@ @@ @@ @@@@@ @@ @@ @ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @ @@ @@ @@ @@ @@ @@ @@ @@@ @ @@ @@ @@ @@ @@ @@ @@@ @@@ @@ @ @@@@ @@@@ @@@@ @@@ @@@ @@@@ @@ @@ @@@ @@ @@@@ Mapping Standard Cells Alliance CAD System 4.0.6, scmap 4.0.9 [1999/11/09] Copyright (c) 1990-2001, ASIM/LIP6/UPMC E-mail support: alliance-support@asim.lip6.fr ================================ Environment ================================ MBK_WORK_LIB = . MBK_CATA_LIB = .:/usr/local/alliance/archi/Cygwin/cells/sclib:/usr/local/ alliance/archi/Cygwin/cells/padlib MBK_TARGET_LIB = /usr/local/alliance/archi/Cygwin/cells/sclib MBK_IN_LO = vst MBK_OUT_LO = vst ======================= Files, Options and Parameters ======================= VHDL file = halfadder.vbe output file = halfadder1.vst Parameter file = default.lax Mode = Mapping standard cell Optimization mode = 50% area - 50% delay optimization Optimization level = 2 ============================================================================ === Compiling 'halfadder' ... Running Standard Cell Mapping ============================= INITIAL COST ================================== Total number of literals = 6 Number of reduced literals = 8 Number of latches = 0 Maximum logical depth = 2 Maximum delay = 1.000 ============================================================================ === Compiling library '/usr/local/alliance/archi/Cygwin/cells/sclib' Generating Expert System ... Cell 'cmx2_y' Unused Cell 'cry_y' Unused Cell 'sum_y' Unused Cell 'tie_y' Unused addOper : Warning operator already exists -> not1 Compile : Warning on 'zbli_y.vbe' --> Cell already declared with another entity 142 rules generated .. ============================== FINAL COST =================================== Number of cells used = 3 Number of gates used = 4 Number of inverters = 2 Number of grids = 280728 Depth max. (gates) = 2 (eq. neg. gates) = 3 ============================================================================ === MBK Driving './halfadder1.vst'... Now, what I am concerned about are the two warnings: addOper : Warning operator already exists -> not1 Compile : Warning on 'zbli_y.vbe' ==> Cell already declared with another entity What are the probable causes of these warnings and how can I resolve them? I just copied the halfader.vbe file as well as the halfadder.c file and followed all the instructions on your tutorial up to scmap. Hoping for your immediate response. Thank you very much! :-) *~~~~~~~~~~~~~~~~~~~~~~~~~~~~* MARLA A. CUYUGAN Science Research Specialist II Advanced Science and Technology Institute

 



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