CMOS technology provides two types of transistors: n-channel transistors that use negatively-charged electrons for current, and p-channel transistors that conduct current by means of positively-charged holes.
CMOS structures have become the primary switching devices in high-density IC design because:
Any logic gate can be constructed from a combination of nMOS and pMOS transistors in a common substrate. Figure 1 shows the functional description, the gate representation, the truth table, the transistor network and, the standard cells in Alliance for (a) an inverter, (b) a two-input NAND gate, and (c) a two-input NOR gate.
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(a) Inverter | |
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(b) Two-input NAND gate | |
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(c) Two-input NOR gate | |
Figure 1. Basic gates. |
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These networks establish the foundation for building larger circuits since all Boolean functions can be implemented in terms of AND, OR, and NOT.
Figure 2 shows the partitioning approach to the design when using Alliance:
Figure 2. Alliance's first partitioning approach
Usually at the core level, the leaf cells of the design belong to the Alliance standard cells library and describe the logical functions needed to design the circuit.. At the chip level, the previous core and pads belonging to the Alliance pad library are used.
The circuit netlist will be captured in two steps:
Alliance does not uses a schematic editor for netlist capture, but rather a textual approach. To do so, Alliance handles among others the following file formats:
Legend | Meaning |
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At the command line give the command that appear immediately after this symbol. |
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Edit and save into a file, all that appears after this symbol. |
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Explanation of a topic |
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Set the environmental variables as shown immediately after this symbol. |
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The text or picture following this symbol appears on the monitor. |
[2] WESTE, N.H.E., ESHRAGHIAN, K. "Principles of CMOS VLSI Design - A Systems Perspective", Second Edition , Addison-Wesley Publishing Company, 1993.