On Sat, 22 Jan 2000, John Price wrote: > Hi. Sorry that this is such an easy question, but I've gone through all > the tutorials, and I have not figured this one out... > > I'm taking a VHDL class, and I understand that alliance supports a subset > if the VHDL language. I'm trying to use a VHDL design with alliance, but > it's not working. > > Is it true that you can have ONLY ONE entity block and ONLY ONE > architecture block per file? If not, how do I have more than one? I keep > getting errors when I try to add another. > > So if that is true, how do I make the tools read in all the files? > > I admit that I am new at this, so please bare with me. > > Thanx, > John You better start looking at the mannuals: $ man vbe $ man vst $ man MBK_CATA_LIB (and maybe some others) jorge.