I tried to compile the following and got this from vasy: --> Run VHDL Compiler --> Compile file codegen Error line 39 : parse error vbl_bcomp.yac 2736 : Error 18 line 39 :illegal concurrent statement What's wrong? phma
-- A latch for a code generator, and other stuff related to direct-sequence spread spectrum entity codegen is port( signal clk: in bit; -- Clock input at 76 MHz signal din: in bit_vector(7 downto 0); -- Input from data lines of ROM signal dout: out bit_vector(7 downto 0); -- Output to address lines of ROM signal tifout: out bit; -- Transmitted intermediate frequency signal clkout: out bit; signal slipsync: in bit -- Edge causes chip clock to slip ); end codegen; architecture behavior of codegen is signal latch: bit_vector(7 downto 0); signal counter: bit_vector(6 downto 0); signal carries: bit_vector(6 downto 0); signal chipclk: bit; signal slipclk: bit; -- clk with an occasional pulse removed signal slipinternal: bit; signal slopinternal: bit; begin dout <= latch; tifout <= counter(5); clkout <= chipclk; state: process(chipclk) begin if (chipclk'event and chipclk) then latch <= din; end if; end process state; slideclock: process(clk,slipsync) begin if (slipsync'event and not slipsync) then slipinternal=1; end if; if (clk'event and slipinternal and not clk) then slopinternal=1; slipinternal=0; end if; if (clk'event and slopinternal and not clk) then slopinternal=0; end if; slipclk=clk and not slopinternal; end process slideclock; count: process(slipclk) begin if (slipclk'event and slipclk) then carries(0)=1; carries(6 downto 1)=carries(5 downto 0) and counter(5 downto 0); counter(6 downto 0)=counter(6 downto 0) xor carries(6 downto 0); chipclk=counter(4); end process count; end behavior;