Hello, I have attached a VHDL code below. I tried compiling this behavioural model but could not. I just want to know if the below can be done? If yes, the method. Thanking you, Niranjan. ----------------------------------------------------------------------- ENTITY mul IS PORT ( a,b : IN BIT_VECTOR(0 to 1); x : OUT BIT_VECTOR(0 to 2) ); END mul; ARCHITECTURE multi OF mul IS BEGIN x(0) <= (a(0) AND b(0)); x(1) <= (( a(1) AND b(0) ) XOR ( a(0) AND b(1) )); x(2) <= (( a(1) AND b(1) ) XOR ( ( a(1) AND b(0) ) AND ( b(1) AND a(0) ))); END multi; ENTITY comp IS PORT ( ina,inb : IN BIT_VECTOR (0 to 1); out : OUT BIT_VECTOR (0 to 1) ); END comp; ARCHITECTURE comp OF comp IS COMPONENT mul PORT ( a,b : IN BIT_VECTOR (0 to 1); x : OUT BIT_VECTOR (0 to 1) ); END COMPONENT; BEGIN u1 : mul PORT MAP (a,b,out); END comp;