Dear Sir/Madam I'm an undergraduate student, studying in the university of Adelaide located in Australia. We're currently running a digital VLSI course using the tool Alliance you people have developed. It'a very nice tool and I have managed to do most of the design. Now, here is the problem. I have a control logic block created by using scr, and a data-path block created by using dpr. There are two lots of RAM blocks generated by rage. The next step is to join all of these 4 blocks into one large block. I've joined the two RAM blocks by using bbr, and joined the control logic block and data-path block by using bbr again. Now there are two new blocks created by above process, and they have to be joined together as well. But i am not successful in doing so by using bbr again. Is it possible to use bbr again on blocks which are generated by bbr? I have attached a copy of source files i have been working on. Plus a list of commands, which i have been using. The last step of commands trying to use bbr to join the last two blocks is un successful. Please indicate me the way of doing the last step. Thanks for your kind support. Regards, Tae Youn.