rage - Random Acess Memory(RAM) Generator
This software belongs to the ALLIANCE CAD system from the CAO-VLSI team at
ASIM/LIP6/UPMC laboratory.
LIP6/ASIM
University P. et M. Curie
4, place Jussieu
75252 PARIS Cedex 05
FRANCE
Fax : {33/0} 1.44.27.62.86
E-mail support : alliance-support@asim.lip6.fr
rage bits words [ -n | -m | -w ] [ -u ] [ -tn ] [ -ckup / -ckdown ] [ -layout ] [ -physicalbox ] [ -vhdl ] [ -datasheet ] [ -icon ] [ -o blockname ]
rage generates several different views of a Random Acess Memory. The ram generated is always constitued of two ram-cells blocks between which is placed a decoder cell.
The interfaces of the ram are given below(there is two versions of the
interface because input and output data can be bidirectionnal or separated):
bidirectionnal data:
ENTITY rage IS
PORT(adr: IN BIT_VECTOR(0 TO n);
data: INOUT BIT_VECTOR(0 TO w);
ck: IN BIT;
write: IN BIT;
en: IN BIT;
vdd: IN BIT;
vss: IN BIT);
END rage;
unidirectionnal data:
ENTITY rage IS
PORT(adr: IN BIT_VECTOR(0 TO n);
din: IN BIT_VECTOR(0 TO w);
dout: OUT BIT_VECTOR(0 TO w);
ck: IN BIT;
write: IN BIT;
en: IN BIT;
vdd: IN BIT;
vss: IN BIT);
END rage;
Write is active high and en is active high. When ck is high for -ckup option RAMs or ck is low for -ckdown option RAMS the RAM is in precharge state, otherwise it is evaluation (read or write mode). The en signal suspends the normal functionment of the RAM by disabling it when it is `0'. In this case the RAM remains in precharge mode. It is authorised to change only at the precharge state of the clock.
All the cells within any generated RAM have been tested and are correct except for one cell which is the memory cell which introduces a design rule violation due to its proper design. The cell dtram_c has an apparent design rule violation. To perform a well DRC on the whole generated RAM one have to copy a `light' version of this cell called dtram2_c in the current work directory and change its name to dtram_c so that the DRC program will take this one first. For most tested target technologies, the translation of this cell from symbolic to real gives a good result. In some cases, one have to patch the cell. However, to avoid any problem one can follow a process of generation. This process is in fact the default process. The cell dtram_c" must be translated to the target technology before translating all the RAM. This cell has a `G' option into the CATAL file instead of `C' option. That means that this cell must not be translated because the real layout view already exist. So it have to be integrated into the global figure (i.e. generated RAM). Perform the following operations:
s2r dtram_c
<patch the cell>
<make a real DRC on the cell>
s2r <ram>
The appropriate RDS_TECHNO_NAME, RDS_IN, RDS_OUT environment variables setting is explained in S2R(3) . For more informations about the tools used to perform this operation, please see S2R(3) .
rage 64 1024 -m -u -layout -vhdl -datasheet -o memo
produces the layout and vhdl views of a 1K size ram of 64-bits word , medium aspect/ratio and separated data buses named memo and provides informations about its function, timing and layout charachteristics.
MBK_CATA_LIB(1) , MBK_WORK_LIB(1) , MBK_OUT_PH(1) , MBK_OUT_LO(1) , MBK_IN_PH(1) ,
This tool is under development at the ASIM/LIP6/UPMC laboratory, cao-vlsi
research team.
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