Hi Thanks for your prompt answer. The description, ff : block (CLK = '1' and not CLK'STABLE) begin dff_r <= guarded d when (enable = '1') else dff_r ; end block; q <= dff_r; does work. However, it instantiates a flip-flop without enable, with additional logic from q to d to correctly implement the enable functionality, such as the following: auxsc4 : nand2b2 PORT MAP ( vss => vss, vdd => vdd, o => auxsc4, i1 => auxsc3, i0 => auxsc2); auxsc3 : and2 PORT MAP ( vss => vss, vdd => vdd, o => auxsc3, i1 => d, i0 => enable); auxsc2 : and2b1 PORT MAP ( vss => vss, vdd => vdd, o => auxsc2, i1 => enable, i0 => q); dff_r : fd PORT MAP ( vss => vss, vdd => vdd, q => q, c => clk, d => auxsc4); What I really want to do is to include in the library a leaf cell which is a flip-flop with enable, so that the above specification can be mapped to only ONE cell. I could not find one in the distributed libraries. When I try to write one myself and include it in the MBK_TARGET_LIB, such as the following: ARCHITECTURE rtl OF dff IS SIGNAL dff_s : REG_BIT REGISTER; BEGIN ASSERT ((vdd and not (vss)) = '1') REPORT "power supply is missing on dff" SEVERITY WARNING; flipflop : BLOCK (c = '1' and not (c'STABLE)) BEGIN dff_s <= guarded d when (ce = '1') else dff_s ; END BLOCK flipflop; q <= dff_s; END; Then, I get the following compiling error from scmap: Compiling library '/usr/local/alliance/archi/Cygwin/cells/xilib' Generating Expert System ... [main] c:\usr\local\alliance\archi\Cygwin\bin\scmap.exe 1000 (0) handle_exceptio ns: Exception: STATUS_ACCESS_VIOLATION [main] scmap 1000 (0) handle_exceptions: Dumping stack trace to scmap.exe.core Any help is welcome. Thanks again, Horacio Neto hcn@inesc.pt Ludovic JACOMME writes: > Hi, > > On Sat, Sep 19, 1970 at 04:20:08PM +0100, Horacio Neto wrote: > > > > Hello > > > > Is there a way to define (in the logic level library: *.vbe files) > > and instantiate a Flip-Flop with Enable (using scmap)? > > > > Descriptions such as the following (in the tutorial file > > "dlxm_chip.vbe") do not work: > > VHDL : Error - bad usage of the 'stable' attribut > > *** Compilation aborted... > > > > trap_v : block (CKFRZ_S = '0' and not CKFRZ_S'STABLE and WENTVR_S = '1') > > begin > > TVR_R <= guarded RESULT_S; > > end block; > > > > Thanks in advance, > > Write you flipflop like this, and it should work better : > > trap_v : block (CKFRZ_S = '0' and not CKFRZ_S'STABLE) > begin > TVR_R <= guarded RESULT_S when (WENTVR_S = '1') else > TVR_R; > end block; > > Regards, Ludo. > > > > -- > > > > Horacio Neto > > e-mail: hcn@inesc.pt > > INESC - Instituto de Engenharia de Sistemas e Computadores > > Rua Alves Redol, 9, 1000 Lisboa - PORTUGAL > > Phone: + 351 21 3100366 > > Fax: + 351 21 3145843 > > -- > > (_) ___ Ludovic JACOMME > _ _ ( ) > ( ) ( ) ( 6 ) Laboratoire LIP6, Equipe ASIM > ( ) (_) ( _ ) Couloir 55-65, 2eme etage, > ( )___ ( ) Universite P. et M. Curie (P6) > (_____) (_) 4 place Jussieu, 75252 Paris Cedex 05 > > Tel: (33) 01.44.27.54.15 > Fax: (33) 01.44.27.72.80 > ICQ: 62526530 > > mailto: Ludovic.Jacomme@asim.lip6.fr > http: //asim.lip6.fr/~ludo > > >