Hi, thank you very much for your help but I am still getting the same type of message. Do you think that maybe this version of Syf that I am working with has some kind of bug? Do you know if there is any kind of limitation in the number of states that is possible to describe in the syf tool? Regards, Adriano Sarmento Ludovic JACOMME wrote: > On Wed, Nov 24, 1999 at 10:37:06AM -0200, Adriano Sarmento wrote: > > Hello, > > I am currently using Alliance 3.0 and I need to synthesize a Control > > Unit that uses a Finite State Machine. But every time I try to use the > > syf tool I get the following message : > > syf: Number of states is zero > > > > Could you tell me why this is happening, please? Just in case I am > > sending the file I want to synthesize. > > > > Thank you, > > > > Adriano Sarmento > > The file uc.vhd you have send us had VHDL syntaxicals errors > but i have corrected all for you ... > Syf support only one case statement on the current_state signals. > I have modified all others case statement in your description. > An End if was missing a the end of the second VHDL process. > (I have also corrected it) > The new description attached to this mail, is correct for Syf > but there are some errors left. > For example The state SRET3 is not used, and all FSM outputs are not > assigned by all states. > > Regards, > > (_) ___ Ludovic JACOMME > _ _ ( ) > ( ) ( ) ( 6 ) Laboratoire LIP6, Equipe ASIM > ( ) (_) ( _ ) Couloir 55-65, 2eme etage, > ( )___ ( ) Universite P. et M. Curie (P6) > (_____) (_) 4 place Jussieu, 75252 Paris Cedex 05 > > Tel: (33) 01.44.27.54.15 > Fax: (33) 01.44.27.72.80 > > e-mail: Ludovic.Jacomme@asim.lip6.fr > > ------------------------------------------------------------------------ > > uc.fsmName: uc.fsm > Type: Plain Text (text/plain)