The design example consists of two phases. The first phase will describe and synthesize the behavior of the half adder. In the second phase the half adder will be used to describe the structure of a full adder (the core of the chip), and then synthesize it.
Figure 1. 1-bit half adder.
In this phase you will:
halfadder.vbe
).
halfadder.pat
).
halfadderl.vst
).
halfadderl.ap
).
Figure 2. Design Flow for the Half Adder component.
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mkdir FullAdder
|
Change into this directory:
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cd FullAdder
|
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Before starting the design you will have to set the environmental variables as
shown below so that you will not run into problems later.
The
The
The
The
The |
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source /usr/local/alliance/share/etc/alc_env.csh
|
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The behavioral description is done using the
Alliance VHDL behavioral subset.
Only concurrent statements are supported. No sequential statements are allowed.
More details are available in the man pages (man vbe ). We begin our
design by describing the behavior of the signals in the half adder.
Create with the "pico" editor a file called
|
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--*************************************************************************** --* * --* Example 1, part A: RTL description for a 1-bit Half Adder * --* * --* Departamento de Ingenieria Electronica * --* Pontificia Universidad Javeriana - CALI * --* * --*************************************************************************** -- Purpose: asimut simulation -- File: halfadder.vbe -- Date: March 7, 1998 -- Version: v1.00 -- Resource: -- Delay units: Zero delay -- -- Author History |Last Touched |Reason: -- Tek --*************************************************************************** -- External ports ENTITY halfadder IS PORT ( A, B, Vdd, Vss: IN BIT; Sum, Carry: OUT BIT ); END halfadder; --*************************************************************************** -- Internal Behaviour ARCHITECTURE halfadder_data_flow OF halfadder IS SIGNAL A_bar, B_bar: BIT; BEGIN A_bar <= NOT A; B_bar <= NOT B; Sum <= ( A_bar AND B ) OR ( A AND B_bar ); Carry <= A AND B; END halfadder_data_flow; |
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asimut is a logical simulation tool for hardware descriptions.
It compiles and loads a VHDL description, which may be behavioral
or structural. Only the VHDL subset discussed above is supported.
Information on asimut's command line parameters, options,
environmental variables required are available in the man pages
(man asimut ).
Any typographical or syntax error in a behavioral description can be found when the file is passed through asimut. |
Give the following command at the command line:
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asimut -b -c halfadder
-b - behavioral option -c - compile |
The following is typically displayed.
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[user@eelabX FullAdder]% asimut -b -c halfadder @ @@@@ @ @ @@@@@@@@@@ @ @ @@ @@@ @ @@ @ @@@ @@ @ @ @ @@ @ @@@ @@@ @@@ @@ @@@ @@@ @@@@ @@ @ @@ @@@@ @@@@ @@@ @@ @@ @@ @@ @@ @ @@ @@@@ @@ @@ @@ @@ @@ @@ @@ @ @@ @@@ @@ @@ @@ @@ @@ @@ @@ @@@@@@@ @ @@ @@ @@ @@ @@ @@ @@ @@ @ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @ @@ @@@ @ @@ @@ @@ @@ @@ @@@ @@ @@@@ @@@@ @ @@@@ @@@@@@ @@@@ @@@ @@@ @@@@ @@ @@@@@@ A SIMUlation Tool Alliance CAD System 3.2b, asimut v2.01 Copyright (c) 1991-1998, ASIM/LIP6/UPMC E-mail support: alliance-support@asim.lip6.fr Paris, France, Europe, Earth, Solar system, Milky Way, ... Initializing ... Searching `halfadder` ... BEH : Compiling `halfadder.vbe` (Behaviour) ... Making GEX ... [user@eelabX FullAdder]% |
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If the above step functions without giving syntax errors then the behavioral
description is ready for simulation.
A file with the test patterns in the pat format is required for the simulation. The pat format file has a declaration part and a description part of the signals. The declaration part consists of a list of inputs, outputs, internal signals and registers of the design. Inputs are forced to a particular value while the outputs are observed during a simulation.
genpat uses a set of C functions that allows a procedural description
of input patterns file for the logic simulator asimut. The genpat
command accepts a C file as input and produces a pattern description
file as output. Information on the functions that are allowed in genpat
is given in the man pages ( |
Create a file called halfadder.c
and enter the following as is:
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/***************************************************************************** * * * Example 1, part A: Generation of test patterns for the 1-bit Half Adder * * * * Departamento de Ingenieria Electronica * * Pontificia Universidad Javeriana - CALI * * * ****************************************************************************/ /* Purpose: Generate test patterns for the 1-bit HA */ /* File: halfadder.c */ /* Date: March 7, 1998 */ /* Version: v1.00 */ /* Resource: */ /* */ /* Author History |Last Touched |Reason: */ /* Tek */ #include <stdio.h> #include <genpat.h> /**************************************************************************** Define the number of test patterns */ #define MAXCYCLE 4 /**************************************************************************** Allocate a memory buffer, convert the first parameter into a string and return the pointer to it. */ char *inttostr ( int integer, int len ) { char *str; str = ( char * ) mbkalloc ( len * sizeof ( char ) + 1 ); sprintf ( str, "%.32d", integer ); return ( &str [32 - len] ); } /**************************************************************************** Starting from the first pattern, apply power signals to the device */ void power ( void ) { AFFECT ( inttostr ( 0, 32 ), "Vdd", "0b1" ); AFFECT ( inttostr ( 0, 32 ), "Vss", "0b0" ); } /**************************************************************************** Generate the truth table for the 1-bit half adder */ void operands ( void ) { int i, a, b, sum, carry; carry = 0; for ( i = 0; i < MAXCYCLE; i++ ) { LABEL ( "pat" ); if ( i % 4 < 2 ) a = 0; else a = 1; AFFECT ( inttostr ( i, 32 ), "A", inttostr ( a, 32 ) ); if ( i % 2 == 0 ) b = 0; else b = 1; AFFECT ( inttostr ( i, 32 ), "B", inttostr ( b, 32 ) ); sum = a + b; AFFECT ( inttostr ( i, 32 ), "Sum", inttostr ( sum % 2, 32 ) ); if ( sum > 1 ) carry = 1; AFFECT ( inttostr ( i, 32 ), "Carry", inttostr ( carry, 32 ) ); } } int main ( void ) { /* Declares the name of the pattern file */ DEF_GENPAT ( "halfadder" ); /* Declare the name, format and type of each of the inputs/outputs */ DECLAR ( "Vdd", ":0", "B", IN, "" ); DECLAR ( "Vss", ":5", "B", IN, "" ); DECLAR ( "A", ":2", "B", IN, "" ); DECLAR ( "B", ":2", "B", IN, "" ); DECLAR ( "Sum", ":2", "B", OUT, "" ); DECLAR ( "Carry", ":2", "B", OUT, "" ); /* Generate the patterns */ power (); operands (); /* Save the pattern file */ SAV_GENPAT (); /* Return success code */ exit ( 0 ); } |
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genpat -v halfadder
-v - verbose option |
The pattern file is generated with .pat
extension.
This command typically generates the following display.
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[user@eelabX FullAdder]% genpat -v halfadder @@@@ @ @@@@@@@ @@ @@ @@ @@ @ @@ @ @@ @@ @@ @@ @@@@@ @@@ @@@ @@ @@ @@@@ @@ @@ @ @ @@@ @ @@ @@ @@ @ @@@@@@@@ @@ @@@@@ @@ @@ @@ @@ @@@@@ @@ @@ @@ @@ @ @@ @@@@@@@@@ @@ @@ @@ @@@@@ @@ @@ @ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@@ @@ @ @@@@ @@@@ @@@@ @@@@ @@@@@@ @@@@ @@ @@@@ Procedural GENeration of test PATterns Alliance CAD System 3.2b, genpat 3.1 Copyright (c) 1991-1998, ASIM/LIP6/UPMC E-mail support: alliance-support@asim.lip6.fr Generating the Makefile Compiling, ... Current execution environment MBK_CATA_LIB : .:/usr/local/alliance/archi/Linux_elf/cells/sclib:/usr/local/al liance/archi/Linux_elf/cells/padlib MBK_WORK_LIB : . MBK_IN_LO : vst MBK_OUT_LO : vst MBK_IN_PH : ap MBK_OUT_PH : ap MBK_CATAL_NAME : CATAL Executing ... Removing tmp files ... [user@eelabX FullAdder]% |
Examine the generated pattern file using the more command.
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more halfadder.pat
|
or give the following command to see a graphical waveform:
![]() |
xpat &
|
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A new window is opened. Choose the File menu from the menu bar and choose
the open option from the menu that pops up. Another sub window inside the
main window will be opened. In this window the files with the extension
.pat will be listed. Choose the halfadder.pat file and
press the ok button. The corresponding waveform will appear on the screen.
|
Should you want, edit the halfadder.pat
file using the text editor
and change the 0
s to 1
s or viceversa to modify the test
patterns.
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asimut -b halfadder halfadder r1
-b - chooses the behavioral simulation option first halfadder - |
The following screen is typically displayed:
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[user@eelabX FullAdder]% asimut -b halfadder halfadder r1 @ @@@@ @ @ @@@@@@@@@@ @ @ @@ @@@ @ @@ @ @@@ @@ @ @ @ @@ @ @@@ @@@ @@@ @@ @@@ @@@ @@@@ @@ @ @@ @@@@ @@@@ @@@ @@ @@ @@ @@ @@ @ @@ @@@@ @@ @@ @@ @@ @@ @@ @@ @ @@ @@@ @@ @@ @@ @@ @@ @@ @@ @@@@@@@ @ @@ @@ @@ @@ @@ @@ @@ @@ @ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @ @@ @@@ @ @@ @@ @@ @@ @@ @@@ @@ @@@@ @@@@ @ @@@@ @@@@@@ @@@@ @@@ @@@ @@@@ @@ @@@@@@ A SIMUlation Tool Alliance CAD System 3.2b, asimut v2.01 Copyright (c) 1991-1998, ASIM/LIP6/UPMC E-mail support: alliance-support@asim.lip6.fr Paris, France, Europe, Earth, Solar system, Milky Way, ... Initializing ... Searching `halfadder` ... BEH : Compiling `halfadder.vbe` (Behaviour) ... Making GEX ... Searching pattern file : `halfadder` ... Restoring ... Linking ... ###----- processing pattern 0 -----### ###----- processing pattern 1 -----### ###----- processing pattern 2 -----### ###----- processing pattern 3 -----### [user@eelabX FullAdder]% |
You can see the simulation result in the file r1.pat
. To see this
file use xpat:
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xpat &
|
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The description given in the halfadder.vbe file is synthesized to
the logical and structural descriptions using scmap. Since the circuit
is very simple, we will map it to the standard cell library directly without
doing any optimizations. Detailed information on scmap is available in
the man pages (man scmap ).
|
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scmap halfadder halfadderl
|
The following is typically displayed:
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[user@eelabX FullAdder]% scmap halfadder halfadderl @@@@ @ @@@@ @ @ @@ @@ @@ @@ @ @@ @ @@@ @@ @ @@@ @@ @@@ @@@@ @@@ @@@ @@@@ @@ @@@ @@ @@ @@ @ @@@ @@ @@@@ @@ @@ @@ @@ @@ @@ @@ @@ @@@ @@ @@ @@ @@ @@@@@ @@ @@ @ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @ @@ @@ @@ @@ @@ @@ @@ @@@ @ @@ @@ @@ @@ @@ @@ @@@ @@@ @@ @ @@@@ @@@@ @@@@ @@@ @@@ @@@@ @@ @@ @@@ @@ @@@@ Mapping Standard Cells Alliance CAD System 3.2b, scmap 4.20 [1997/10/09] Copyright (c) 1990-1998, ASIM/LIP6/UPMC E-mail support: alliance-support@asim.lip6.fr ================================ Environment ================================ MBK_WORK_LIB = . MBK_CATA_LIB = .:/usr/local/alliance/archi/Linux_elf/cells/sclib:/usr/lo cal/alliance/archi/Linux_elf/cells/padlib MBK_TARGET_LIB = /usr/local/alliance/archi/Linux_elf/cells/sclib MBK_IN_LO = vst MBK_OUT_LO = vst ======================= Files, Options and Parameters ======================= VHDL file = halfadder.vbe output file = halfadderl.vst Parameter file = default.lax Mode = Mapping standard cell Optimization mode = 50% area - 50% delay optimization Optimization level = 2 =============================================================================== Compiling 'halfadder' ... Running Standard Cell Mapping ============================= INITIAL COST ================================== Total number of literals = 6 Number of reduced literals = 8 Number of latches = 0 Maximum logical depth = 2 Maximum delay = 1.000 =============================================================================== Compiling library '/usr/local/alliance/archi/Linux_elf/cells/sclib' Generating Expert System ... Cell 'cmx2_y' Unused Cell 'cry_y' Unused Cell 'sum_y' Unused Cell 'tie_y' Unused 162 rules generated .. ============================== FINAL COST =================================== Number of cells used = 3 Number of gates used = 4 Number of inverters = 2 Number of grids = 3276 Depth max. (gates) = 2 (eq. neg. gates) = 2 =============================================================================== MBK Driving './halfadderl.vst'... [user@eelabX FullAdder]% |
The structural file can be examined by giving the Unix "more" command:
![]() |
more halfadderl.vst
|
to see the structural description generated by scmap. The corresponding schematic is shown in Figure 3 below.
Figure 3. Synthesized 1-bit half adder.
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You can do the simulation of the structural description with the same pattern files that were used for the behavioral description. |
To do the simulation on the structural description, give the following command at the command prompt.
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asimut halfadderl halfadder r2
no option - takes the structural description by default halfadderl - |
The following screen is typically displayed
![]() |
[user@eelabX FullAdder]% asimut halfadderl halfadder r2 @ @@@@ @ @ @@@@@@@@@@ @ @ @@ @@@ @ @@ @ @@@ @@ @ @ @ @@ @ @@@ @@@ @@@ @@ @@@ @@@ @@@@ @@ @ @@ @@@@ @@@@ @@@ @@ @@ @@ @@ @@ @ @@ @@@@ @@ @@ @@ @@ @@ @@ @@ @ @@ @@@ @@ @@ @@ @@ @@ @@ @@ @@@@@@@ @ @@ @@ @@ @@ @@ @@ @@ @@ @ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @ @@ @@@ @ @@ @@ @@ @@ @@ @@@ @@ @@@@ @@@@ @ @@@@ @@@@@@ @@@@ @@@ @@@ @@@@ @@ @@@@@@ A SIMUlation Tool Alliance CAD System 3.2b, asimut v2.01 Copyright (c) 1991-1998, ASIM/LIP6/UPMC E-mail support: alliance-support@asim.lip6.fr Paris, France, Europe, Earth, Solar system, Milky Way, ... Initializing ... Searching `halfadderl` ... Compiling `halfadderl` (Structural) ... Flattening the root figure ... Searching `a2_y` ... BEH : Compiling `a2_y.vbe` (Behaviour) ... Making GEX ... Searching `annup_y` ... BEH : Compiling `annup_y.vbe` (Behaviour) ... Making GEX ... Searching `n1_y` ... BEH : Compiling `n1_y.vbe` (Behaviour) ... Making GEX ... Searching pattern file : `halfadder` ... Restoring ... Linking ... ###----- processing pattern 0 -----### ###----- processing pattern 1 -----### ###----- processing pattern 2 -----### ###----- processing pattern 3 -----### [user@eelabX FullAdder]% |
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The structural description created above has been created without worrying
about the standard cells fanout limits and critical path signals. glop
can analyze the structural description and create a new description by adding
buffers to the appropriate nets so as to solve fanout problems and to optimize
on signal delays. However, at this moment we are not concerned about this.
Detailed information on glop is available in the man pages
(man glop ).
|
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The Standard Cell Router scr is used to place and route the core of the
halfadderl.vst file. This creates a file with extension
.ap . More information on scr is available in the man pages
(man scr ).
|
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scr -p -r -i 1000 halfadderl
-p - invokes the automatic placement process -r - invokes the automatic routing process -i - iteration number to improve the placement quality |
The following is typically displayed.
![]() |
[user@eelabX FullAdder]% scr -p -r -i 1000 halfadderl @@@@ @ @@@@ @ @@@@@@@ @ @@ @@ @@ @@ @@ @@ @ @@ @ @@ @@ @@@ @@ @ @@ @@ @@@@ @@ @@ @@ @@@@ @@ @@@@@ @@@ @@ @@ @@ @ @@ @@ @@ @@ @@ @@ @@ @ @@ @@ @@@ @ @@ @@ @@ @@ @ @@@@ @@@@ @@@@@ @@@ Standard Cell router Alliance CAD System 3.2b, scr 5.2 Copyright (c) 1991-1998, ASIM/LIP6/UPMC E-mail support: alliance-support@asim.lip6.fr Loading logical view : halfadderl Placing logical view : halfadderl Loading SCP data base ... Generating initial placement ... 4 cells 8 nets in 1 rows Placement in process of treatment : 100% 9% saved in 3.0 s Saving placement 100% Checking consistency between logical and physical views Loading SCR data base ... Deleting MBK data base ... Global routing ... Channel routing ... |_____Routing Channel : scr_p2 |_____Routing Channel : scr_p4 Making vertical power and ground wires Saving layout : halfadderl [user@eelabX FullAdder]% |
halfadderl.ap
we use graal,
a symbolic layout editor.
Give the command
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graal &
|
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A new window is opened. Choose the File menu from the menu bar and choose
the open option from the menu that pops up. Another sub window inside the
main window will be opened. In this window the files with the extension
.ap will be listed. Choose the halfadderl.ap file and
press the ok button. The layout will appear on the screen, but only at
the standard cell level:
|
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![]() |
Figure 4. Layout of the half adder. |
---|
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Now you can choose the Tool option from the menu bar and from the pop-up menu choose the peek option. Now with the mouse mark the window where you want to "peek" at the layout. If the whole layout is "peek"ed typically you will see the layout as shown below: |
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Figure 5. Flattened layout of the half adder. |
---|
This completes the design of the half adder component.
Figure 6. 1-bit full adder.
The behavioral description focuses on block behavior. Figure 7 shows how two instances of the same building block, the half adder, can be used to implement a full adder using an structural approach.
![]() | |
(a) Block diagram composition of the full adder | |
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|
(b) Top level block diagram of the full adder | |
Figure 7. Internal and external block diagram views of the 1-bit full adder. |
---|
In this phase you will complete the proposed design:
fulladder.vst
) using the previously designed half-adder.
fulladder.pat
).
fulladder.ap
).
fulladder.ap
).
fulladder.cif
).
Figure 8. Design Flow for the Full Adder.
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The structural description is done using the
Alliance VHDL structural subset.
Create with the "pico" editor a file called |
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--*************************************************************************** --* * --* Example 1, part B: Structural description for a 1-bit Full Adder * --* * --* Departamento de Ingenieria Electronica * --* Pontificia Universidad Javeriana - CALI * --* * --*************************************************************************** -- Purpose: asimut simulation and synthesis -- File: fulladder.vst -- Date: March 7, 1998 -- Version: v1.00 -- Resource: ABDALLAH, Nizar, Second Regional Course on Advanced VLSI -- Design Techniques. ICTP-UNU-Microprocessor Laboratory. -- Medellin, Colombia, 9 - 27 February 1998. -- Delay units: Zero delay -- -- Author History |Last Touched |Reason: -- Tek --*************************************************************************** -- External ports ENTITY fulladder IS PORT ( A, B, Cin, Vdd, Vss: IN BIT; Sum, Cout: OUT BIT ); END fulladder; --*************************************************************************** -- Internal Structure ARCHITECTURE fulladder_structural OF fulladder IS -- Declare components to use COMPONENT halfadderl PORT ( A: IN BIT; B: IN BIT; Sum: OUT BIT; Carry: OUT BIT; Vdd: IN BIT; Vss: IN BIT ); END COMPONENT; COMPONENT o2_y PORT ( i0: IN BIT; i1: IN BIT; t: OUT BIT; vdd: IN BIT; vss: IN BIT ); END COMPONENT; -- Declare internal signals SIGNAL c1, s1, c2: BIT; BEGIN -- Instantiate components and connect them ha1: halfadderl PORT MAP ( Vss => Vss, Vdd => Vdd, A => A, B => B, Sum => s1, Carry => c1 ); ha2: halfadderl PORT MAP ( Vss => Vss, Vdd => Vdd, A => s1, B => Cin, Sum => Sum, Carry => c2 ); or1: o2_y PORT MAP ( vss => Vss, vdd => Vdd, i0 => c1, i1 => c2, t => Cout ); END fulladder_structural; |
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Any typographical or syntax error in a structural description can be found when the file is passed through asimut. |
Give the following command at the command line:
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asimut -c fulladder
-c - compile |
The following is typically displayed.
![]() |
[user@eelabX FullAdder]% asimut -c fulladder @ @@@@ @ @ @@@@@@@@@@ @ @ @@ @@@ @ @@ @ @@@ @@ @ @ @ @@ @ @@@ @@@ @@@ @@ @@@ @@@ @@@@ @@ @ @@ @@@@ @@@@ @@@ @@ @@ @@ @@ @@ @ @@ @@@@ @@ @@ @@ @@ @@ @@ @@ @ @@ @@@ @@ @@ @@ @@ @@ @@ @@ @@@@@@@ @ @@ @@ @@ @@ @@ @@ @@ @@ @ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @ @@ @@@ @ @@ @@ @@ @@ @@ @@@ @@ @@@@ @@@@ @ @@@@ @@@@@@ @@@@ @@@ @@@ @@@@ @@ @@@@@@ A SIMUlation Tool Alliance CAD System 3.2b, asimut v2.01 Copyright (c) 1991-1998, ASIM/LIP6/UPMC E-mail support: alliance-support@asim.lip6.fr Paris, France, Europe, Earth, Solar system, Milky Way, ... Initializing ... Searching `fulladder` ... Compiling `fulladder` (Structural) ... Flattening the root figure ... Searching `a2_y` ... BEH : Compiling `a2_y.vbe` (Behaviour) ... Making GEX ... Searching `annup_y` ... BEH : Compiling `annup_y.vbe` (Behaviour) ... Making GEX ... Searching `n1_y` ... BEH : Compiling `n1_y.vbe` (Behaviour) ... Making GEX ... Searching `o2_y` ... BEH : Compiling `o2_y.vbe` (Behaviour) ... Making GEX ... [user@eelabX FullAdder]% |
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If the above step functions without giving syntax errors then the structural description is ready for simulation. |
Create a file called fulladder.c
and enter the following as is:
![]() |
/***************************************************************************** * * * Example 1, part B: Generation of test patterns for the 1-bit Full Adder * * * * Departamento de Ingenieria Electronica * * Pontificia Universidad Javeriana - CALI * * * ****************************************************************************/ /* Purpose: Generate test patterns for the 1-bit FA */ /* File: fulladder.c */ /* Date: March 7, 1998 */ /* Version: v1.00 */ /* Resource: */ /* */ /* Author History |Last Touched |Reason: */ /* Tek */ #include <stdio.h> #include <genpat.h> /***************************************************************************** Define the number of test patterns */ #define MAXCYCLE 8 /***************************************************************************** Allocate a memory buffer, convert the first parameter into a string and return the pointer to it. */ char *inttostr ( int integer, int len ) { char *str; str = ( char * ) mbkalloc ( len * sizeof ( char ) + 1 ); sprintf ( str, "%.32d", integer ); return ( &str [32 - len] ); } /***************************************************************************** Starting from the first pattern, apply power signals to the device */ void power ( void ) { AFFECT ( inttostr ( 0, 32 ), "Vdd", "0b1" ); AFFECT ( inttostr ( 0, 32 ), "Vss", "0b0" ); } /***************************************************************************** Generate the truth table for the 1-bit full adder */ void operands ( void ) { int i, a, b, cin, sum, cout; for ( i = 0; i < MAXCYCLE; i++ ) { LABEL ( "pat" ); if ( i % 8 < 4 ) a = 0; else a = 1; AFFECT ( inttostr ( i, 32 ), "A", inttostr ( a, 32 ) ); if ( i % 4 < 2 ) b = 0; else b = 1; AFFECT ( inttostr ( i, 32 ), "B", inttostr ( b, 32 ) ); if ( i % 2 == 0 ) cin = 0; else cin = 1; AFFECT ( inttostr ( i, 32 ), "Cin", inttostr ( cin, 32 ) ); sum = a + b + cin; AFFECT ( inttostr ( i, 32 ), "Sum", inttostr ( sum % 2, 32 ) ); if ( sum > 1 ) cout = 1; else cout = 0; AFFECT ( inttostr ( i, 32 ), "Cout", inttostr ( cout % 2, 32 ) ); } } int main ( void ) { /* Declares the name of the pattern file */ DEF_GENPAT ( "fulladder" ); /* Declare the name, format and type of each of the inputs/outputs */ DECLAR ( "Vdd", ":0", "B", IN, "" ); DECLAR ( "Vss", ":5", "B", IN, "" ); DECLAR ( "A", ":2", "B", IN, "" ); DECLAR ( "B", ":2", "B", IN, "" ); DECLAR ( "Cin", ":3", "B", IN, "" ); DECLAR ( "Sum", ":2", "B", OUT, "" ); DECLAR ( "Cout", ":2", "B", OUT, "" ); /* Generate the patterns */ power (); operands (); /* Save the pattern file */ SAV_GENPAT (); /* Return success code */ exit ( 0 ); } |
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genpat -v fulladder
-v - verbose option |
This command typically generates the following display.
![]() |
[user@eelabX FullAdder]% genpat -v fulladder @@@@ @ @@@@@@@ @@ @@ @@ @@ @ @@ @ @@ @@ @@ @@ @@@@@ @@@ @@@ @@ @@ @@@@ @@ @@ @ @ @@@ @ @@ @@ @@ @ @@@@@@@@ @@ @@@@@ @@ @@ @@ @@ @@@@@ @@ @@ @@ @@ @ @@ @@@@@@@@@ @@ @@ @@ @@@@@ @@ @@ @ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@@ @@ @ @@@@ @@@@ @@@@ @@@@ @@@@@@ @@@@ @@ @@@@ Procedural GENeration of test PATterns Alliance CAD System 3.2b, genpat 3.1 Copyright (c) 1991-1998, ASIM/LIP6/UPMC E-mail support: alliance-support@asim.lip6.fr Generating the Makefile Compiling, ... Current execution environment MBK_CATA_LIB : .:/usr/local/alliance/archi/Linux_elf/cells/sclib:/usr/local/al liance/archi/Linux_elf/cells/padlib MBK_WORK_LIB : . MBK_IN_LO : vst MBK_OUT_LO : vst MBK_IN_PH : ap MBK_OUT_PH : ap MBK_CATAL_NAME : CATAL Executing ... Removing tmp files ... [user@eelabX FullAdder]% |
Examine the generated pattern file using the more command.
![]() |
more fulladder.pat
|
or give the following command to see a graphical waveform:
![]() |
xpat &
|
Should you want, edit the fulladder.pat
file using the text editor
and change the 0
s to 1
s or viceversa to modify the
test patterns.
![]() |
asimut fulladder fulladder r3
no option - chooses the structural simulation option first halfadder - |
The following screen is typically displayed:
![]() |
[user@eelabX FullAdder]% asimut fulladder fulladder r3 @ @@@@ @ @ @@@@@@@@@@ @ @ @@ @@@ @ @@ @ @@@ @@ @ @ @ @@ @ @@@ @@@ @@@ @@ @@@ @@@ @@@@ @@ @ @@ @@@@ @@@@ @@@ @@ @@ @@ @@ @@ @ @@ @@@@ @@ @@ @@ @@ @@ @@ @@ @ @@ @@@ @@ @@ @@ @@ @@ @@ @@ @@@@@@@ @ @@ @@ @@ @@ @@ @@ @@ @@ @ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @ @@ @@@ @ @@ @@ @@ @@ @@ @@@ @@ @@@@ @@@@ @ @@@@ @@@@@@ @@@@ @@@ @@@ @@@@ @@ @@@@@@ A SIMUlation Tool Alliance CAD System 3.2b, asimut v2.01 Copyright (c) 1991-1998, ASIM/LIP6/UPMC E-mail support: alliance-support@asim.lip6.fr Paris, France, Europe, Earth, Solar system, Milky Way, ... Initializing ... Searching `fulladder` ... Compiling `fulladder` (Structural) ... Flattening the root figure ... Searching `a2_y` ... BEH : Compiling `a2_y.vbe` (Behaviour) ... Making GEX ... Searching `annup_y` ... BEH : Compiling `annup_y.vbe` (Behaviour) ... Making GEX ... Searching `n1_y` ... BEH : Compiling `n1_y.vbe` (Behaviour) ... Making GEX ... Searching `o2_y` ... BEH : Compiling `o2_y.vbe` (Behaviour) ... Making GEX ... Searching pattern file : `fulladder` ... Restoring ... Linking ... ###----- processing pattern 0 -----### ###----- processing pattern 1 -----### ###----- processing pattern 2 -----### ###----- processing pattern 3 -----### ###----- processing pattern 4 -----### ###----- processing pattern 5 -----### ###----- processing pattern 6 -----### ###----- processing pattern 7 -----### [user@eelabX FullAdder]% |
You can see the simulation result in the file r3.pat
. To see this
file use xpat:
![]() |
xpat &
|
fulladder.vst
file. This
creates a file with extension .ap
. More information on scr
is available in the man pages (man scr
).
![]() |
scr -p -r -l 2 -i 1000 fulladder
-p - invokes the automatic placement process -r - invokes the automatic routing process -l - specifies the number of rows to use -i - iteration number to improve the placement quality |
The following is typically displayed.
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[user@eelabX FullAdder]% scr -p -r -l 2 -i 1000 fulladder @@@@ @ @@@@ @ @@@@@@@ @ @@ @@ @@ @@ @@ @@ @ @@ @ @@ @@ @@@ @@ @ @@ @@ @@@@ @@ @@ @@ @@@@ @@ @@@@@ @@@ @@ @@ @@ @ @@ @@ @@ @@ @@ @@ @@ @ @@ @@ @@@ @ @@ @@ @@ @@ @ @@@@ @@@@ @@@@@ @@@ Standard Cell router Alliance CAD System 3.2b, scr 5.2 Copyright (c) 1991-1998, ASIM/LIP6/UPMC E-mail support: alliance-support@asim.lip6.fr Loading logical view : fulladder Placing logical view : fulladder Loading SCP data base ... Generating initial placement ... 9 cells 14 nets in 2 rows Placement in process of treatment : 100% 59% saved in 3.6 s Saving placement 100% Checking consistency between logical and physical views Loading SCR data base ... Deleting MBK data base ... Global routing ... Channel routing ... |_____Routing Channel : scr_p2 |_____Routing Channel : scr_p4 |_____Routing Channel : scr_p6 Making vertical power and ground wires Saving layout : fulladder [user@eelabX FullAdder]% |
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The Design Rule Checker druc is a general parameterized VLSI design
rule checker used to check the conformance of the fulladder.ap
layout to the technology's design rules.
The default mode of druc is (currently) full flat: it first flattens
all the hierarchy in order to obtain a flat, rectangle level description.
If design errors are found, druc produces the list of them in
More information on druc is available in the man pages ( |
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druc fulladder
|
The following is typically displayed.
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[user@eelabX FullAdder]% druc fulladder @@@@@@@ @@@@@@@ @@@@ @ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @ @@ @@ @@ @@ @@@ @@@@ @@ @ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@@@@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @ @@ @@ @@ @@ @@ @@@ @@ @@ @@@@@@@ @@@@@ @@@ @@@@ @@ @@@@ Design Rule Checker Alliance CAD System 3.2b, druc 3.00 Copyright (c) 1993-1998, ASIM/LIP6/UPMC E-mail support: alliance-support@asim.lip6.fr Flatten DRC on: fulladder Delete MBK figure : fulladder Load Flatten Rules : /usr/local/alliance/archi/Linux_elf/etc/cmos_7.rds Unify : fulladder Create Ring : fulladder_rng Merge Errorfiles: Merge Error Instances: instructionCourante : 50 End DRC on: fulladder Saving the Error file figure Done 0 File: fulladder.drc is empty: no errors detected. [user@eelabX FullAdder]% |
fulladder.ap
, we use graal.
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graal &
|
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Figure 9. Symbolic layout of the full adder. |
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Figure 10. Flattened layout of the full adder. |
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This completes the design of the full adder's core.
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Until now all the files describe the circuit only as symbolic cells. The foundry
requires the layout of the core described in terms of rectangles and layers in
the gds or cif format. This can be done in Alliance using s2r;
the goal of s2r is to perform the translation from the symbolic layout to
physical layout for the foundry. It uses a technology file whose name is defined
by the environnement variable RDS_TECHNO_NAME .
More information on s2r is available in the man pages ( |
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s2r -v fulladder fulladder
-v - verbose mode on first fulladder - |
This invocation will produce the full adder real layout from the standard cell
library without connectors, in cif format (fulladder.cif
).
The following is typically displayed.
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[user@eelabX FullAdder]% s2r -v fulladder fulladder @@@@ @ @@ @@ @@ @@@@@@ @@@ @@ @@@ @@@ @@ @ @ @@ @@@ @@ @@@ @ @@ @@ @@@@ @ @@ @@@@ @ @@ @ @@@ @ @ @@ @@ @@ @@@@@@ @@ @ @@@@@ @@@@@@@ @@@@ Symbolic to Real layout converter Alliance CAD System 3.2b, s2r 3.6 Copyright (c) 1991-1998, ASIM/LIP6/UPMC E-mail support: alliance-support@asim.lip6.fr o loading technology file : /usr/local/alliance/archi/Linux_elf/etc/cmos_7.rds o loading all level of symbolic layout : fulladder o removing symbolic data structure o layout post-treating with connectors, with scotchs. --> post-treating model a2_y rectangle merging : --> post-treating model n1_y rectangle merging : --> post-treating model tie_y rectangle merging : --> post-treating model annup_y rectangle merging : --> post-treating model o2_y rectangle merging : --> post-treating model fulladder ring flattenning : rectangle merging : o saving fulladder.gds o memory allocation informations --> required rectangles = 0 really allocated = 0 --> required scotchs = 0 really created = 0 --> Number of allocated bytes: 37282 [user@eelabX FullAdder]% |
fulladder.cif
, we use dreal.
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dreal &
|
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A new window is opened. Choose the File menu from the menu bar and choose
the open option from the menu that pops up. Another sub window inside the
main window will be opened. In this window the files with the extension
.cif will be listed. Choose the fulladder.cif file and
press the ok button. The layout will appear on the screen, but only at
the standard cell level:
|
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Figure 11. Real layout of the full adder. |
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Now you can choose the Tool option from the menu bar and from the pop-up menu choose the Flatten option. Typically you will see the layout as shown below: |
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Figure 12. Real (flattened) layout of the full adder. |
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This completes the design of the 1-bit full adder core.