Table of Contents
alliance tools - Index of Alliance Tools
This software belongs to the ALLIANCE CAD system from the CAO-VLSI team at
ASIM/LIP6/UPMC laboratory.
LIP6/ASIM
University P. et M. Curie
4, place Jussieu
75252 PARIS Cedex 05
FRANCE
Fax : {33/0} 1.44.27.62.86
E-mail support : alliance-support@asim.lip6.fr
- AMG(1)
- - Array Multiplior Generator
- DLX_ASM(1)
- - assembly language for DLX processor
- DPR(1)
- - Placer-Router for Datapath Compiler
- DRuC(1)
- - Design Rule Checker
- MBK_CATAL_NAME(1)
- - define the mbk catalog file
- MBK_CATA_LIB(1)
- - define the mbk catalog directory
- MBK_IN_LO(1)
- - define the logical input format of mbk and genlib
- MBK_IN_PH(1)
- - define the physical input format of mbk and genlib
- MBK_OUT_LO(1)
- - define the logical output format of mbk and genlib
- MBK_OUT_PH(1)
- - define the physical output format of mbk and genlib
- MBK_SEPAR(1)
- - define the separator character for hierarchy
- MBK_VDD(1)
- - define the high level power name pattern
- MBK_VSS(1)
- - define the ground power name pattern
- MBK_WORK_LIB(1)
- - define the mbk working directory
- RDS_IN(1)
- - define the real layout input file format of rds
- RDS_OUT(1)
- - define the real layout output format of rds
RDS_TECHNO_NAME(1)
- define the rds technology file
- RING(1)
- - PAD RING router
- SYF(1)
- - Finite State Machine synthesizer.
- abl(1)
- - Prefixed representation for boolean functions
- alcbanner(1)
- - Display a standardized banner for Alliance tools
- asimut(1)
- - A simulation tool for hardware descriptions
- aut(1)
- - Memory allocation, and hash tables management
- bbr(1)
- - A pitchless channel router for preplaced two blocks
floorplan
- bdd(1)
- - Mutli Reduced Ordered Binary Decision Diagrams
- bdd(1)
- - Ordered binary decision diagrams representation
- bgd(1)
- - register file generator
- bop(1)
- - boolean optimization of a logic level behavioural
description (VHDL data flow)
- bsg(1)
- - Barrel Shifter Generator
- buseg(1)
- - Tristate generator for FITPATH data-path compiler.
- c4map(1)
- - mapping of a behavioural description with the CMOS
Complex Cell Compiler : C4.
- dpp(1)
- - DataPath Placement tool
- dreal(1)
- - Graphic real layout viewer
- etas(1)
- - A timing file .dtx and .ttx browser
- fpgen(1)
- - Procedural language for Data-Path synthesis based
upon C.
- fpmap(1)
- - fpga mapper of a logic level behavioural description
(VHDL data flow)
- fsm(1)
- - Finite State Machine representation.
- genlib(1)
- - Procedural design language based upon C, along with
its compiler
- genpat(1)
- - A procedural pattern file generator(1)
- genscan(1)
- - scan path generator
- genview(1)
- - genlib graphical source level debugger
- glop(1)
- - Fanout optimizer, global optimizer and timing analyzer
of a gate netlist
- graal(1)
- - symbolic layout editor
- grog(1)
- - a generic ROM generator
- l2p(1)
- - Creates a PostScript file from a symbolic layout
file,or from a physical layout file.
- librds(1)
- - rds library description
- librfm(1)
- - rfm library description
- librpr(1)
- - rpr library description
- librtl(1)
- - rtl library description
- librut(1)
- - rut library description
- librwi(1)
- - rwi library description
- log(1)
- - logical representations for boolean functions and
utilities.
- lvx(1)
- - Logical Versus eXtracted net-list comparator
- lynx(1)
- - Hierarchical netlist extractor
- mbk(1)
- - generic layout and netlist data structures
- mbk2ps(1)
- - Creates a PostScript file from a symbolic layout
cell
- mbkcif(1)
- - mbk cif translater
- pat2dwl(1)
- - pattern translator from ALLIANCE CAD SYSTEM to HILO
CAD SYSTEM
- patest(1)
- - a pattern translator for test.
- proof(1)
- - Formal proof between two behavioural descriptions
- rage(1)
- - Random Acess Memory(RAM) Generator
- rds(1)
- - rds package
- rfg(1)
- - register file generator
- rsa(1)
- - Recurrence Solver Adder generator
- s2r(1)
- - Process mapping from symbolic layout to physical
layout
- scmap(1)
- - mapping of a behavioural description onto a standard
cell library.
- scr(1)
- - Standard Cell Router
- tas(1)
- - A switch level static timing analyzer for CMOS circuits
- xmbk(1)
- - A simple way to set alliance environnement variables
- YAGLE(1)
- - Functional abstraction of CMOS circuits
This tool is under development at the ASIM/LIP6/UPMC laboratory, cao-vlsi
research team.
We need your feedbak to improve documentation and tools.
If you find bugs, please fill-in the form at
http://asim.lip6.fr/alliance/support/bug-report/
Thanks for doing this.
Table of Contents
Alliance Web Site © 1997, 2002 ASIM/LIP6/UPMC,
page maintained by Czo [Olivier Sirol]
, last updated on 26 May 2000.