This software belongs to the ALLIANCE CAD system from the CAO-VLSI team at
ASIM/LIP6/UPMC laboratory.
LIP6/ASIM
University P. et M. Curie
4, place Jussieu
75252 PARIS Cedex 05
FRANCE
Fax : {33/0} 1.44.27.62.86
E-mail support : alliance-support@asim.lip6.fr
buseg - Tristate generator for FITPATH data-path compiler.
buseg <dpwidth> <opwidth> <lsb_slice>
[-msb0] <-vhdl|-netlist|-icon> [-o ModelName]
lsb_slice An integer giving the operator bottom slice, i.e. the slice where the LSB will be set.
msb0
If this switch is present, the virtual connector with index of
n is on the slice numberred Width-1-n. That is to say :
- Connectors indexed zero are on the slice Width-1.
- Connectors indexed Width-1 are on the slice zero.
Otherwise, the virtual connector with index of n is on the
slice numberred n. That give :
- Connectors indexed zero are on the slice zero.
- Connectors indexed Width-1 are on the slice Width-1.
So if we assume that the MSB is in all case associated with the
slice numberred Width-1, when msb0 is set the connector of the MSB
have an index of zero, and an index of Width-1 otherwise.
Notice that the leaf cell indexation is not affected by the
msb0 switch.
ModelName Give the name of the model. If it is not specified the generator creates it automatically (based on the parametrization).
Buseg generate the netlist view and/or the icon view of the tristate operator. In order to build the netlist view the generator use the following cells of fplib librarie :
Terminals
i0[opwidth+lsb_slice-1:lsb_slice]
i0[dpwidth-opwidth-lsb_slice:dpwidth-lsb_slice-1]
Input bus, virtual terminal (without and with the -msb0 option).
o[opwidth+lsb_slice-1:lsb_slice]
o[dpwidth-opwidth-lsb_slice:dpwidth-lsb_slice-1]
Ouput bus, virtual terminal (without and with the -msb0 option).
vdd, vss Power supplies.
buseg 32 32 0 -netlist -o my_tris
Generates the netlist of a 32 bits tristate, named my_tris, with leaf
cell indexed from slice 0 (LSB) to slice 31 (MSB).
buseg 32 16 16 -netlist
Generate the netlist of a 16 bits tristate, named buse32x16x16l_cl,
with leaf cell indexed from slice 16 (LSB) to slice 31 (MSB).
DP_BUSE(3) , fpgen(3) , fplib(3) , mbk(3)
This tool is under development at the ASIM/LIP6/UPMC laboratory, cao-vlsi
research team.
We need your feedbak to improve documentation and tools.
If you find bugs, please fill-in the form at
http://asim.lip6.fr/alliance/support/bug-report/
Thanks for doing this.