alliance-support '2000
VASY problem...


Örjan Gustavsson (orjan@switchcore.com)
Thu, 27 Apr 2000 23:35:52 +0200

What am I doing wrong? I am trying to translate some very simple VHDL examples with VASY/ASIMUT. So far none of my tests have worked, due to errors in the vbe file generated by vasy. (At least asimut seems to think there is errors :-) Since I am using the tools to learn VHDL, my confidence in my own code is not that high. I'm attaching the original vhdl input to vasy, the generated vbe file and the error messages from asimut. Regards, Örjan Gustavsson

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity tst is port ( a, b : in unsigned (7 downto 0); ck : in std_logic; q : out unsigned (7 downto 0) ); end tst; architecture behaviour of tst is begin -- behaviour process begin wait until ck'event and ck = '1'; q <= a xor b; end process; end behaviour;

ENTITY tst IS PORT( a : IN BIT_VECTOR(7 DOWNTO 0); b : IN BIT_VECTOR(7 DOWNTO 0); ck : IN BIT; q : OUT REG_VECTOR(7 DOWNTO 0) REGISTER ); END tst; ARCHITECTURE VBE OF tst IS BEGIN LABEL0 : BLOCK ((ck = '1') AND NOT(ck'STABLE) ) BEGIN q <= GUARDED (a XOR b); END BLOCK LABEL0; END VBE;

orjan@fingolfin:~/work/alliance/cpu99 > asimut -c -b tst_v @ @@@@ @ @ @@@@@@@@@@ @ @ @@ @@@ @ @@ @ @@@ @@ @ @ @ @@ @ @@@ @@@ @@@ @@ @@@ @@@ @@@@ @@ @ @@ @@@@ @@@@ @@@ @@ @@ @@ @@ @@ @ @@ @@@@ @@ @@ @@ @@ @@ @@ @@ @ @@ @@@ @@ @@ @@ @@ @@ @@ @@ @@@@@@@ @ @@ @@ @@ @@ @@ @@ @@ @@ @ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @ @@ @@@ @ @@ @@ @@ @@ @@ @@@ @@ @@@@ @@@@ @ @@@@ @@@@@@ @@@@ @@@ @@@ @@@@ @@ @@@@@@ A SIMUlation Tool Alliance CAD System 4.0.6, asimut v3.02 Copyright (c) 1991...1999-2000, ASIM/LIP6/UPMC E-mail support: alliance-support@asim.lip6.fr Paris, France, Europe, Earth, Solar system, Milky Way, ... initializing ... searching `tst_v` ... BEH : Compiling `tst_v.vbe` (Behaviour) ... `tst_v.vbe` Error 5 line 6 :illegal port declaration (mode, type, kind) `tst_v.vbe` Error 17 line 16 :`q` unknown port or signal making GEX ...

 



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