alliance-support '2000
Re: SOME QUESTIONS


Ludovic JACOMME (Ludovic.JACOMME@asim.lip6.fr)
Fri, 23 Jun 2000 11:30:56 +0200

Hi Gianluca, On Thu, Jun 22, 2000 at 09:19:39PM +0200, Gianluca Cornetta wrote: > Hi, > > I am using alliance 4.0.6 and i have found the following probless: > > if i try to use GRAAL the following error message appears: > > rpr:rprparse.704 error calu1 unexpected line 89 > in technological file > /users2/scratch/cornetta/alliance/archi/Solaris/etc/cmos_11.rds The file cmos_11.rds is not part of the 4.0.6 alliance distribution, but of the latest (and unstable) version, that's why it doesn't work. > > I have solved this problem by commenting the following environment variables in the > configuration script: > > DREAL_TECHNO_NAME > GRAAL_TECHNO_NAME > GENVIEW_TECHNO_NAME > RDS_TECHNO_NAME > ELP_TECHNO_NAME > > Doing so GRAAL works perfectly however I would like to implement a differential > family of standard cell using the 0.35u process that comes with your package. > How can i do that? In fact, with Alliance all cells are symbolic (in lambda) and you choose the process you want (0.35micron etc ...) at the end of the design flow, by using S2R with your .rds technological file (prol035.rds etc ...). But during the design flow, if you want to extract a netlist or check design rules with the parameters of a particular technology, you can specify it using the RDS_TECHNO_NAME environment variable. (prol035.rds or prol10.rds etc ...) > > Moreover I would like to know if LYNX is know able to extract layout for all > kind of processes and not only for a 1u process. If it is possible how may > configure it for the aforementioned 0.35u process. Yes, (from the beginning ...) Lynx is able to extract layout for all processes. (using the RDS_TECHNO_NAME environment variable). > > Also i vave seen that LYNX only create the netlist but does not attach the SPICE > parameters, why? What do you mean by SPICE parameters ? > > I have designed some new standard cells and i would like to use them collecting > into a new library, how can i do that? I suppose that i must create a file that > specifies for each cell input and output pins, in order to use these cell with > GENLIB language. I wonder how can i do that and which is the format of such > file. You can put all your cells in a particular directory. You have also to create a CATAL file containing the list of all your cells. (see catal(5)) You have also to create a .vbe and .al file for each cell, describing respectively the behavior and transistor netlist of the cell (if you want to use ASIMUT/Yagle/Tas on a circuit containing your cells) > > Thank you very much for your attention. > > Best regards, > > --Gianluca Cornetta Regards, (_) ___ Ludovic JACOMME _ _ ( ) ( ) ( ) ( 6 ) Laboratoire LIP6, Equipe ASIM ( ) (_) ( _ ) Couloir 55-65, 2eme etage, ( )___ ( ) Universite P. et M. Curie (P6) (_____) (_) 4 place Jussieu, 75252 Paris Cedex 05 Tel: (33) 01.44.27.54.15 Fax: (33) 01.44.27.72.80 ICQ: 62526530 mailto: Ludovic.Jacomme@asim.lip6.fr http: //asim.lip6.fr/~ludo

 



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