I noticed that the documentation for the cell libraries was a bit sparse, so I took the time to write up basic cell descriptions for the standard-cell library. This should make it a bit easier to find cells. - Guy
sclib Cell Documentation Explanation of Tables
This table attempts to provide a brief description of each cell, to assist designers in selecting the appropriate cell. The exact description of each cell is in that cell's VHDL model.Logic Elements
Cell Name | Inputs | Outputs | Function | Description |
a2_y | 2 | 1 | AND | |
a2p_y | 2 | 1 | AND | |
a3_y | 3 | 1 | AND | |
a3p_y | 3 | 1 | AND | |
a4_y | 4 | 1 | AND | |
a4p_y | 4 | 1 | AND | |
annup_y | 4 | 1 | OR->NAND | |
b1_y | 1 | 1 | buffer | |
cmx2_y | 4 | 1 | AND->OR | |
cry_y | 3 | 1 | carry gen? | |
d1_y | 1 | 1 | buffer | |
mx2_y | 4 | 1 | AND->OR | |
mx2p_y | 4 | 1 | AND->OR | |
mx3_y | 6 | 1 | AND->OR | |
mx4_y | 8 | 1 | AND->OR | |
n1_y | 1 | 1 | inverter | |
na2_y | 2 | 1 | NAND | |
na2p_y | 2 | 1 | NAND | |
na3_y | 3 | 1 | NAND | |
na3p_y | 3 | 1 | NAND | |
na4_y | 4 | 1 | NAND | |
nao3_y | 3 | 1 | NAND->OR | |
nao4_y | 4 | 1 | NAND->OR | |
ndrv_y | 1 | 1 | inverter | |
nmx2_y | ||||
no2_y | 2 | 1 | NOR | |
no3_y | 3 | 1 | NOR | |
noa3_y | 3 | 1 | NOR->AND | |
noa4_y | 4 | 1 | NOR->AND | |
nop2_y | 2 | 1 | NOR | |
nop3_y | 3 | 1 | NOR | |
noue4_y | 4 | 1 | OR->AND | |
np1_y | 1 | 1 | inverter | |
nxr2_y | 2 | 1 | XOR | |
o2_y | 2 | 1 | OR | |
o3_y | 3 | 1 | OR | |
one_y | 0 | 1 | logic 1 | |
op2_y | 2 | 1 | OR | |
op3_y | 2 | 1 | OR | |
p1_y | 1 | 1 | buffer | |
sum_y | 4 | 1 | sum gen? | |
tie_y | 0 | 0 | ||
ts_y | 2 | 1 | tristate buf | |
tsn_y | 2 | 1 | tristate buf | |
tsp_y | 2 | 1 | tristate buf | |
xr2_y | 2 | 1 | XOR | |
zbli_y | 1 | 1 | inverter | |
zero_y | 0 | 1 | logic 0 |
Cell Name | Inputs | Outputs | Function | Description |
l1_y | 2 | 1 | latch | |
l1n_y | 2 | 1 | latch | |
l1x_y | 2 | 2 | latch | |
l2_y | 4 | 1 | latch | 2-port latch |
l2n_y | 4 | 1 | latch | |
l3_y | 6 | 1 | latch | 3-port latch |
l3r_y | 5 | 1 | latch | 2-port latch w/ clear |
l3s_y | 5 | 1 | latch | 2-port latch w/ set |
l4_y | 8 | 1 | latch | 4-port latch |
l4r_y | 7 | 1 | latch | 3-port latch w/ clear |
l4s_y | 7 | 1 | latch | 3-port latch w/ set |
l5_y | 10 | 1 | latch | 5-port latch |
l5r_y | 9 | 1 | latch | 4-port latch w/ clear |
l5s_y | 9 | 1 | latch | 4-port latch w/ set |
l6r_y | 11 | 1 | latch | 5-port latch w/ clear |
l6s_y | 11 | 1 | latch | 5-port latch w/ set |
ms2_y | 4 | 1 | flop | flop w/ 2-input mux |
ms2n_y | 4 | 1 | flop | flop w/ 2-input mux |
ms2rx_y | ||||
ms2sx_y | ||||
ms2x_y | ||||
ms_y | 2 | 1 | flop | |
msn_y | 2 | 1 | flop | |
msrx_y | 3 | 2 | flop | flop w/ clear |
mssx_y | 3 | 2 | flop | flop w/ set |
msx_y | 3 | 2 | flop | flop w/ set |