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Alliance
is a complete set of free CAD tools and portable
libraries for VLSI design. It includes a VHDL compiler and simulator, logic
synthesis tools, and automatic place and route tools.
A complete set of portable CMOS libraries
is provided, including a RAM generator, a ROM generator
and a data-path compiler. Alliance is the result of a ten
year effort spent at ASIM department of
LIP6 laboratory of the Pierre et
Marie Curie University (Paris VI, France).
Alliance has been used for research projects such as the
875 000 transistors StaCS superscalar microprocessor and
400 000 transistors IEEE Gigabit HSL Router. More... |
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Alliance VLSI CAD System is free software. Binaries, source code and cells libraries are freely available under the GNU General Public License (GPL). You are welcome to use the software package even for commercial designs without any fee. You are just required to mention : "Designed with Alliance © ASIM/LIP6 Université Pierre et Marie Curie"
Latest:
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Please note that documentation and tutorials might not be up to date. Known problems are :
yagle and tas are not part of Alliance anymore, but are now available from Avertec for free for members of academic institutions.
Some man pages in html found at alliance\doc\man\ are wrong, please refer to the real manpages (> man lynx)