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Capture and validation of the structural view

The structural view can be captured once the data flow description is validated. The actual capture of the netlist relies either on specific description languages, genlib for standard cells or fpgen for data-path, or on direct synthesis from the data flow using the bop tool for optimization and the scmap tool to map on a cell library. Genlib and fpgen are netlist-oriented libraries of C functions. In the design methodology, it is essential for the students to get acquainted with the C language basics. The advantage of such an approach is that designers do not have to learn several language with specific syntax and semantics.

Usually, the main behavior is partitionned in several sub-behaviors. Some are described recursively using the genlib language, other using fpgen, and the other ones can be directly synthesized from a VHDL description of the corresponding sub-behaviors. The scmap tool takes an RTL description and generates a netlist of standard cell gates. An other subset of VHDL allows to capture finite state machines. This subset, called fsm, can be translated into a RTL description using the tool syf, and then the resulting description optimized usign bop and finally syntesized as a netlist using once more scmap.

Since asimut can operate on both RTL and structural views, the structural description is checked against the behavioral description by using the same set of patterns that has been used for behavioral validation.


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