Hi, On Thu, Nov 08, 2001 at 04:23:22PM -0800, David Elmore wrote: > Ludovic JACOMME, > We like using the "for generate" statement to construct multiple > objects. Does Alliance VHDL support this construct? Thanks. You can try to use VASY tool. It's a VHDL translator. It tries to translate most common use VHDL substet to Alliance VHDL subset. > > -- > David Elmore > The MicroDisplay Corporation > 3055 Research Drive > San Pablo, Calif. 94806 > Phone: (510)-243-9515 x115 > FAX: (510)-243-9522 > Best regards, (_) ___ Ludovic JACOMME _ _ ( ) ( ) ( ) ( 6 ) Laboratoire LIP6, Equipe ASIM ( ) (_) ( _ ) Couloir 65-66, 4eme etage Porte 405, ( )___ ( ) Universite P. et M. Curie (P6) (_____) (_) 4 place Jussieu, 75252 Paris Cedex 05 Tel: (33) 01.44.27.27.06 01.44.27.54.15 Fax: (33) 01.44.27.72.80 ICQ: 62526530 mailto: Ludovic.Jacomme@asim.lip6.fr http: //www-asim.lip6.fr/~ludo