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Name

grog - a generic ROM generator

Synopsis

grog bits words codefile [ -tr ] [ -hz ] [ -r ] [-msb0] [ -o blockname ] [ -layout ] [ -vhdl ] [ -icon ] [ -logicalbox ] [ -physicalbox ] [ -datasheet ]

Origin

This software belongs to the ALLIANCE CAD system from the CAO-VLSI team at ASIM/LIP6/UPMC laboratory.
LIP6/ASIM
University P. et M. Curie 4, place Jussieu 75252 PARIS Cedex 05 FRANCE
Fax : {33/0} 1.44.27.62.86
E-mail support : alliance-support@asim.lip6.fr

Description

grog is high speed portable ROM generator. The ROM is contact coded, this means than all non used transistors are left with an unconnected drain. This is not an error, but some verification tools may be mixed up. The ROM binary contents is defined in the codefile. This file is a dataflow VHDL description file with vbe extension. In this file, the text after the first WITH/SELECT/WHEN construct is considered as the ROM contents. The constant and concatenation operators are allowed in this description.
A little example is given below :

constant rot
: bit_vector(2 downto 0) := B"101 ;
constant pet
: bit_vector(2 downto 0) := B"110 ;
constant more
: bit_vector(3 downto 0) := B"0100 ;
constant some
: bit_vector(3 downto 0) := B"0001 ;
constant more
: bit_vector(3 downto 0) := B"0100 ;
constant ones
: bit_vector(3 downto 0) := B"1111 ;
constant fred
: bit_vector(7 downto 0) := B"01110111 ; constant other : bit_vector(7 downto 0) := B"10000110 ; constant stuff : bit_vector(7 downto 0) := B"01110101 ;
constant eric
: bit_vector(7 downto 0) := B"10101110 ;

WITH address(5 DOWNTO 0) SELECT
output(0 TO 15) <= some & more & stuff WHEN B"000000", some & other & ones WHEN B"1 & X"F",

fred & eric
WHEN pet & rot,
X"FFFF
WHEN OTHERS; Both the address and the output assigments have to contain the vector ordering explicitly. The least significant bit of the address vector has index 0.

In order to be able to generate any view, the path to grog leaf cells library, grol, must be set correctly. The usual path is /labo/cells/grog, and has to be put in the environment through the use of the MBK_CATA_LIB(1) shell variable. Notice that the leaf cells of the ROM follows a given naming convention, to avoid name collisions when generating the final tape. So, all leaf cells names are prefixed with gr and suffixed with _c.

The ROM interface is described here for behavior description.

ENTITY grog IS
PORT( adr : IN BIT_VECTOR(n DOWNTO 0);

ck
: IN BIT_VECTOR(k DOWNTO 0);
f
: OUT BIT_VECTOR(m DOWNTO 0); vdd : IN BIT; vss : IN BIT ); END grog;

When the number of words is larger than 512, the ck connector is vectorized. In that case, all clock connectors are not internally shorted and must be externally connected to the same signal.

Options

bits
specifies the number of bits per words. The legal values range from 1 to 64 inclusive.
words
specifies the number of words in the rom. The legal values are 64, 128, 256, n * 512, where n ranges from 1 to 8 inclusive.
codefile
gives the name of the file to be used for programming the ROM. The file is expected to have a .vbe extension.
-tr
indicates that a minimum width metal 1 through route is to be placed each every vertical bit slice in the ROM matrix. This through route does not have connectors associated to it, it is just a path to be used by floorplan router if needed.
-hz
indicates that the output buffer is a three-state buffer and not a simple direct buffer. This means that a connector for the three-state control signal called oe, is created. The output is in high impedance when oe is low.
-r
when chosen, this option reverses the topological order of the ouputs. By default, f[0] is on the left hand side of the circuit, the decoder being at the right hand side. Using r indicates that f[0] will be placed on the right hand side.
-msb0
indicates that the most significant bit of the addresses, adr lines, is called adr(0) in the vhdl coding file, thus changing its meaning and the ROM binary contents.
-n blockname
forces the resulting files to have the name name. If not specified, the generator will create a unique name, for a given set of parameters excluding the coding file.
-layout
if stated, will generate the ROM layout.
-vhdl
will output the vhdl description of the coded ROM. A pattern file, for cosimulation purpose, is also created.
-icon
will generate the icon view of the block.
-logicalbox
will generate an interface of the circuit, in terms of connectors, for use with a router. No internal description in terms of gate netlist is generated.
-physicalbox
generates only a layout outline of the ROM. This is of little interest, since the internal layout is not top secret.
-datasheet
outputs some informations in readable form about the ROM, like size, and also an estimation of the propagation delays.

Examples

grog 5 1024 romcode -hz -r -logicalbox -physicalbox This generate a ROM of 1024 words of 5 bits each, with an high impedance output, and lsb first.
The generated views give only the interface of the block.

grog 28 64 dlxm_ctl layout netlist vhdl 1.0 datasheet This generate a ROM of 64 words of 28 bits each, using the dlxm_ctl.vbe file as coding file, and outputs a layout, a netlist, and a datasheet with delay estimations for a 1.0 pF load on f output lines.

Output Files

name.xx
Layout and netlist views. For these views, the suffixes depend on the MBK_OUT_LO(1) and MBK_OUT_PH(1) environment variables. The name is either the one specified by the user, or an internally generated one prefixed by rwordsxbits.
name.vbe
vhdl behavior.
name.pat
Set of patterns for validation.
name.dts
Datasheet.

Environment Variables

MBK_CATA_LIB
contains the directory path of the ROM generator leaf cell library, rolib. This library is by default in /labo/cells/grog, and if not, depends upon the system administrator installation.
MBK_WORK_LIB
contains the directory path of the working directory, usually set to
MBK_IN_PH
contains the format of the ROM generator leaf cell library.
MBK_OUT_PH
contains the expected format of the generated layout.
MBK_OUT_LO
contains the expected format of the netlist output.
ICON_OUT
contains the expected format of the icon output.

See Also

mbk(1) , genlib(1) , rfg(1) , bsg(1) , rsa(1) .

Bug Report

This tool is under development at the ASIM/LIP6/UPMC laboratory, cao-vlsi research team.
We need your feedbak to improve documentation and tools. If you find bugs, please fill-in the form at http://asim.lip6.fr/alliance/support/bug-report/ Thanks for doing this.


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