alliance-support '1997
BUG dpr  : bad vss, vdd name ???


Czo [Olivier SIROL] (Olivier.Sirol@asim.lip6.fr)
Thu, 11 Dec 1997 16:03:43 +0100 (MET)

Begin Alliance bug report 1.2 ------------------------------------------------------------------- Posted on : 1997 December 11 (Thursday at 16:03) MET by : <BUJON_Frederic@mail.dotcom.fr subject : BUG dpr  : bad vss, vdd name ??? version : Alliance 3.2b ------------------------------------------------------------------- Problem description : --------------------- Quand je route avec dpr un datapath, (pas n'importe lequel bien sur), il me nomme les vss et vdd dans le .ap : vss_1, vss_2, vss_3 etc, etc Or, je doit effectuer un BBR plus tard ! Le probleme est que bbr ne routera pas les alimentations entre elle, ni ring je pense, donc j'aurais une partie de circuit non alimenter !! C'est-y normal ??? La marche que je suis est : fpgen ramcore dpr -p -r ramcore -o ramcore Merci Environnement : --------------- Platform : Linux boubou 2.0.32 #4 Sun Dec 7 23:38:49 MET 1997 i586 MBK_CATAL_NAME=CATAL MBK_CATA_LIB=.:/labo/Linux_elf/cells/sclib:/labo/Linux_elf/cells/dplib:/labo/Linux_elf/cells/fplib:/labo/Linux_elf/cells/rfg:/labo/Linux_elf%!!2Fcells/rsa:./colonnes:/labo/Linux_elf/cells/bsg:/labo/Linux_elf/cells/padlib MBK_IN_LO=vst MBK_IN_PH=ap MBK_OUT_LO=vst MBK_OUT_PH=ap MBK_TARGET_LIB=/labo/Linux_elf/cells/sclib MBK_WORK_LIB=. How to reproduce the bug : -------------------------- /* DATAPATH DESCRIPTION OF RAM */ /* HADAMARD Version 2.0 */ /* BUJON FREDERIC 1197 */ /*******************************/ #include "genlib.h" #include "fpgen.h" #define LC DP_LOCON #define DW DEFAULT_WIDTH #define DS DEFAULT_SLICE main() { DP_DEFLOFIG("ramcore",32,LSB_INDEX_ZERO); LC("ck[15:0]",IN,"ck[15:0]"); LC("co3",IN,"co3"); LC("co0",IN,"co0"); LC("coa[2:1]",IN,"coa[2:1]"); LC("cob[2:1]",!!IN,"cob[2:1]"); LC("coc[2:1]",IN,"coc[2:1]"); LC("cod[2:1]",IN,"cod[2:1]"); LC("din[31:0]",IN,"din[31:0]"); LC("ramo[31:0]",OUT,"ramo[31:0]"); LC("wen[15:0]",IN,"wen[15:0]"); LC("vdd",IN,"vdd"); LC("vss",IN,"vss"); /* Debut du carnage */ /* Déclaration des registres (bascules D ici) */ DP_PDFF("ram0",DW,DS,"wen[0]","ck[0]", "din[31:0]", "ram0[31:0]", "niet0[31:0]",EOL); DP_PDFF("ram1",DW,DS,"wen[1]","ck[1]", "din[31:0]", "ram1[31:0]", %0!!9 "niet1[31:0]",EOL); DP_PDFF("ram2",DW,DS,"wen[2]","ck[2]", "din[31:0]", "ram2[31:0]", "niet2[31:0]",EOL); DP_PDFF("ram3",DW,DS,"wen[3]","ck[3]", "din[31:0]", "ram3[31:0]", "niet3[31:0]",EOL); DP_PDFF("ram4",DW,DS,"wen[4]","ck[4]", "din[31:0]", "ram4[31:0]", "niet4[31:0]",EOL); DP_PDFF("ram5",DW,DS,"wen[5]","ck[5]", "din[31:0]", "ram5[31:0]", "niet5[31:0]",EOL); DP_PDFF("ram6",DW,DS,"wen[6]","!!ck[6]", "din[31:0]", "ram6[31:0]", "niet6[31:0]",EOL); DP_PDFF("ram7",DW,DS,"wen[7]","ck[7]", "din[31:0]", "ram7[31:0]", "niet7[31:0]",EOL); DP_PDFF("ram8",DW,DS,"wen[8]","ck[8]", "din[31:0]", "ram8[31:0]", "niet8[31:0]",EOL); DP_PDFF("ram9",DW,DS,"wen[9]","ck[9]", "din[31:0]", "ram9[31:0]", "niet9[31:0]",EOL); DP_PDFF("ram10",DW,DS,"wen[10]","ck[10]", "din[31:0]", "ram10[31:0]", !! "niet10[31:0]",EOL); DP_PDFF("ram11",DW,DS,"wen[11]","ck[11]", "din[31:0]", "ram11[31:0]", "niet11[31:0]",EOL); DP_PDFF("ram12",DW,DS,"wen[12]","ck[12]", "din[31:0]", "ram12[31:0]", "niet12[31:0]",EOL); DP_PDFF("ram13",DW,DS,"wen[13]","ck[13]", "din[31:0]", "ram13[31:0]", "niet13[31:0]",EOL); DP_PDFF("ram14",DW,DS,"wen[14]","ck[14]", "din[31:0]", "ram14[31:0]", "niet14[31:0]",EOL); DP_PDFF("ram15",DW,DS%!!2C"wen[15]","ck[15]", "din[31:0]", "ram15[31:0]", "niet15[31:0]",EOL); /* 1ere etage */ DP_MUX4CS("mux4a",DW,DS,"coa[2:1]", "ram0[7:0]","ram2[7:0]","ram8[7:0]","ram10[7:0]", "ram0[15:8]","ram2[15:8]","ram8[15:8]","ram10[15:8]", "ram0[23:16]","ram2[23:16]","ram8[23:16]","ram10[23:16]", "ram0[31:24]","ram2[31:24]","ram8[31:24]","ram10[31:24]", "muxao[31:0]",EOL); DP_MUX4CS("mux4b",DW,DS,"cob[2:1]", "ram4[7:0]","ram6[7:0]","ram12[7:0]!!","ram14[7:0]", "ram4[15:8]","ram6[15:8]","ram12[15:8]","ram14[15:8]", "ram4[23:16]","ram6[23:16]","ram12[23:16]","ram14[23:16]", "ram4[31:24]","ram6[31:24]","ram12[31:24]","ram14[31:24]", "muxbo[31:0]",EOL); DP_MUX4CS("mux4c",DW,DS,"coc[2:1]", "ram1[7:0]","ram3[7:0]","ram9[7:0]","ram11[7:0]", "ram1[15:8]","ram3[15:8]","ram9[15:8]","ram11[15:8]", "ram1[23:16]","ram3[23:16]","ram9[23:16]","ram11[23:16]", "ram1[31:24]","ram3[31:24]","ram9[31:24]",%!!22ram11[31:24]", "muxco[31:0]",EOL); DP_MUX4CS("mux4d",DW,DS,"cod[2:1]", "ram5[7:0]","ram7[7:0]","ram13[7:0]","ram15[7:0]", "ram5[15:8]","ram7[15:8]","ram13[15:8]","ram15[15:8]", "ram5[23:16]","ram7[23:16]","ram13[23:16]","ram15[23:16]", "ram5[31:24]","ram7[31:24]","ram13[31:24]","ram15[31:24]", "muxdo[31:0]",EOL); /* Deuxieme etage */ DP_MUX4CS("mux4fi",DW,DS, "co3","co0", "muxdo[31:0]", "muxco[31:0]", "muxbo[31:0]", "m!! Finger Information : -------------------- End Alliance bug report 1.2

 



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