alliance-support '2000
Re: VHDL subset


Frédéric Pétrot (Frederic.Petrot@lip6.fr)
Thu, 13 Jan 2000 17:51:20 +0100

On Thu, Jan 13, 2000 at 10:01:30AM -0500, Ian Harris wrote: > Dear Support Team, > Can a generate statement be used in a VHDL description read by alliance? > Thanks for your help. > - Ian Harris > University of Massachusetts, Amherst > harris@ecs.umass.edu Unfortunately not. As you may have noticed, Alliance VHDL subset is quite restricted, and generate are not part of it. Note also that generics are not supported either (which is quite useful for generates) Hacked solutions involve the use of perl or awk (or m4 for the brilliants' ones :-), but this is an other story. Fred -- @----------------------,-,-----,-------------------------------------@ |Ad augusta Frederic PETROT: MC d'ASIM/LIP6/UPMC (Paris VI) | |Per angusta 55-65/201 4 place Jussieu, 75252 Paris Cedex 05 | |Work:331 44275415 Fax:331 44276286 Frederic.Petrot@lip6.fr | |Home:331 47129513 Pager:336 56278636 //asim.lip6.fr/~fred/ | @--------------------------------------------------------------------@

 



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