alliance-support '2000
Vasy question


Stefan Schippers - 5071 (stefan.schippers@st.com)
Tue, 21 Mar 2000 16:19:01 +0100

Hello all, I have tried out the Vasy VHDL analyzer; given the following file as input (adder.vhd) library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; entity adder is port( A : in INTEGER range 0 to 8; B : out INTEGER range 0 to 8); end adder; architecture rtl_1 of adder is begin process( A ) begin B<=A-1; end process; end rtl_1; the Vasy analyzer, called with: vasy -a -I vhd adder.vhd gives the following error: @@@@ @@@ @ @@@@ @ @@@@ @@@@ @@ @ @ @ @@ @@ @ @@ @ @@@ @@ @ @@ @ @@ @ @@@ @@@ @@ @ @@ @ @ @@ @@@@ @@ @@ @ @ @@ @@@@ @@ @@ @ @ @@ @@@ @@ @@@ @@@@@@@ @ @@ @@ @@@ @ @@ @@ @@ @@ @ @ @@ @@@ @ @@ @ @@@@ @@@@ @ @@@@ @@@@@@ VHDL Analysis for Synthesizer Alliance CAD System 4.0.6, vasy 1.05 Copyright (c) 1999-2000, ASIM/LIP6/UPMC Author(s): Ludovic Jacomme Contributor(s): Frederic Petrot E-mail support: alliance-support@asim.lip6.fr --> Run VHDL Compiler --> Compile file adder vasy_simul.420 Elaborate error unconvertible value in line [15] If I change line 15 from: B<=A-1; to: B<=A+1; everything is OK. What is wrong when using a decrement operation? Thank You for the attention! Stefan Schippers stefan.schippers@st.com

 



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