In our VLSI class, we intend to show that VLSI verification is at least as important as VLSI physical design. For that reason, we have introduced in the design flow powerful tools to perform behavior, netlist and layout verifications.
The correctness of the design rules is checked using the design rule checker druc.
An extracted netlist can be obtained from the resulting layout. Lynx, the layout extractor operates on both hierarchical and flattened layout and can output both flattened netlists (transistor netlist) and hierarchical netlists. The transistor netlist is the input of the yagle functional abstractor. Yagle provides a VHDL data-flow behavioral description, identical to the one that feeds asimut, from the transistor netlist of a circuit. The resulting behavior can be compared to the initial specifications using either asimut with the functionnal vectors used for the validation of the behavioral specification, or formally proved equivalent, thanks to the formal proof analyzer proof.
When extracted hierarchically, the resulting netlist can be compared with the original netlist by using the lvx tool. Lvx, that stands for Logical Versus Extracted, is a netlist comparator that matches every design object found in both netlists.
The critical path of the circuit, and an estimate of its delay, can be obtained using the static timming analyzer tas.