alliance-support '02
Re: Width/Type Mismatch


Francois DONNET (francois.donnet@asim.lip6.fr)
Thu, 31 Jan 2002 11:30:55 +0100

Please try this: shift8: shift8 PORT MAP ( vdd => vdd, vss => vss, data_in8 => Data_in, data_out8 =>shifted8, controld => enable & opcode(3) ); GIIE wrote: > Hello sir, > > I am writing a structural description to join various > components (logical shifters) together. In my structural file, I have > the ff as one of my declarations: > shift8: shift8 > PORT MAP ( > vdd => vdd, > vss => vss, > data_in8 => Data_in, > data_out8 =>shifted8, > controld(1) => enable, > controld(0) => opcode(3) > ); > > Upon checking for syntax errors in my code using Asimut, I get the ff > error: > > `lrshift` Error 38 line 72 :width or/and type mismatch > `lrshift` Error 38 line 74 :width or/and type mismatch > `lrshift` Error 38 line 82 :width or/and type mismatch > `lrshift` Error 38 line 84 :width or/and type mismatch > > Where line 72 is : "controld(1) => enable,". > > I would like to know if my above declaration is correct. Controld is a > 2bit "controld(1 downto 0)" input to component shift8. I would like to > connect one of its pins to the 'enable' pin of my main block > (structural description) and the other to one of the 'opcode' pins. > Controld and opcode are declared as bit_vector. Enable is an input to > my main block and its declared as "bit" and opcode(3 downto 0) is a > bit_vector. > The individual components(4) have been verified to work correctly. > > Is my declaration wrong... as in one pin of a 'bit_vector' declaration > cannot be connected to a 'bit' declaration?. > > Thanks > GIIE > > > ----------------------------------------------------------------------- > Do You Yahoo!? > Yahoo! Auctions Great stuff seeking new owners! Bid now!

 



Alliance Web Site © 1997, 2002 ASIM/LIP6/UPMC, page maintained by Czo [Olivier Sirol] , last updated on 01 February 2002.