bgd - register file generator
bgd
bgd -h
bgd -deco crunch_name
bgd bits words busses
[ li ] [ lo ] [ id ] [ lp ] [ wel|weh ] [ dsh|ish ] [ hc ]
ro|rs|ds|ba
[ name=name_prefix ]
layout|outline|vhdl|data|netlist
[ layout ] [ outline ] [ vhdl ] [ data ] [ netlist ]
This software belongs to the ALLIANCE CAD system from the CAO-VLSI team at
ASIM/LIP6/UPMC laboratory.
LIP6/ASIM
University P. et M. Curie
4, place Jussieu
75252 PARIS Cedex 05
FRANCE
Fax : {33/0} 1.44.27.62.86
E-mail support : alliance-support@asim.lip6.fr
This command is available with MBK/GENLIB software installation option.
The first form is a on line help.
The second is a long on line help.
In the third form, bgd decrunch prefix name who have been generated by himself.
In the last form, bgd generates differents views of a register file and offers a very large range of possible parameters. The generator respect the CAO-VLSI definition of a data-path. The slice is fixed at 60 lambdas, allows multi-acces connectors, could be used with the data-path router dpr(1) .
The generator needs a library cells to well compute. The MBK_CATA_LIB environment variable should contain the path to the library, /labo/cells/bgd.
words Number of registers. The range is from 2 to 256, the value must be even.
busses Number of read busses : 1 or 2. Generated register file has one write address bus and one or two read address busses.
name=name_prefix
name_prefix indicate the user name prefix for all files generated.
If no name is given, the default files prefix is : XXYYYYY Where XX
is ro | rs | ds | ba and YYYYY is an encode of the parameter
values ensuring an unique name.
layout To obtain a layout view. The different formats are given by mbk(1) documentation.
outline
To obtain a outline view.
netlist
To obtain a netlist view. This view contains only the logical block
interface. The different formats are given by mbk(1)
documentation.
bgd 24 16 2 rs name=my_reg outline
Produces the outline view of 16 registers of 24 bits with 2 read
busses. The generated file name is my_reg.edif".
bgd 16 32 1 wel ba name=test layout vhdl Produces the layout and vhdl views of a 32 registers of 16 bits complete register file with 1 read bus and a write enable input active at low level. The prefix name of all generated files is test".
Each signal name is predefined and could not be modified by the user. Index 0 is the most significant bit and N represent the number of bits. M represent the size of address busses, this size depend on number of registers. Signal names are :
ad_w[0]-ad_w[M-1]
Write address
ad_r_a[0]-ad_r_a[M-1]
First read address
ad_r_b[0]-ad_r_b[M-1]
Second read address
c_s_a First bypass control signal
c_s_b Second bypass control signal
in_a[0]-in_a[N-1]
Data input
i_s_a[0]-i_s_a[N-1]
First bypass data input
i_s_b[0]-i_s_b[N-1]
Second bypass data input
out_a[0]-out_a[N-1]
Fisrt data output
out_b[0]-out_b[N-1]
Second data output
vdd, vss
Power supplies
The complete register file dimension are approximately :
width = words * 34 lambdas.
height = (bits + 3 * busses + 6) * 60 lambdas.
This tool is under development at the ASIM/LIP6/UPMC laboratory, cao-vlsi
research team.
We need your feedbak to improve documentation and tools.
If you find bugs, please fill-in the form at
http://asim.lip6.fr/alliance/support/bug-report/
Thanks for doing this.