This FSM subset is neither accepted by the logic simulator asimut, nor the formal prover proof.
This VHDL subset is defined to enable classical MOORE and MEALY synchronous
finite state machine description as well as stack FSM description
(see man syf
for further information about this kind of FSM).
A FSM description is made of two and only two processes.
Connectors and signals can only be of IN
, OUT
,
and two user defined enumerated types. Vectors of IN
and
OUT
types are also allowed.
FSM's states and stack control signals must be declared as enumerated type.
For the scan-path, three more signals are required:
scan_test: IN BIT
scan_in: IN BIT
scan_out: OUT BIT
For a ROM implementation, the Vdd
and Vss
signals must
be explicitely declared as:
rom_vdd : IN BIT
rom_vss : IN BIT
These signals, declared in the interface, are not used or assigned in the FSM description.
The '-P' option of syf(1) allows scan-path implementation.
Three pragmas are used, their generic names are:
CLOCK
: External clock signal name.
CURRENT_STATE
: Current State name.
NEXT_STATE
: Next State name.
Ten other pragmas are optional.
SCAN_TEST
: Enable test mode (scan-path).
SCAN_IN
: scan-path input.
SCAN_OUT
: scan-path output.
RETURN_STATE
: Return State name.
CONTROL
: Stack Control signal name.
POP
: POP operation on the stack.
PUSH
: PUSH operation on the stack.
NOP
: NOP operation on the stack.
ROM_VDD
: Name of the Vdd
signal of the ROM.
ROM_VSS
:Name of the Vss
signal of the ROM.
Two different processes are used: The first process, called state process, allows to describe state transition and outputs generation. It is not controlled by the clock. The second process is controlled by the clock and describes the state register and stack registers modifications.
State process sensitivity list contains inputs and CURRENT_STATE
,
it means that the state process is activated when the CURRENT_STATE
or an input signal changes. A CASE
statement is used to describe,
for each state, the next state and outputs.
The second process sensitivity list contains the clock
signal, so
this process is enabled whenever clock changes.
Both Level sensitive latches, and falling edge triggered flip flops can be used for state registers and stack implementation.
ENTITY FSM_Ex IS PORT ( ck : IN BIT; reset : IN BIT; t_mode: IN BIT; s_in : IN BIT; i : IN BIT; s_out : OUT BIT; o : OUT BIT ); End FSM_Ex; ARCHITECTURE auto OF FSM_Ex IS TYPE STATE_TYPE IS ( S0, S1, S2, S3, S4, S5 ); TYPE CONTROL IS ( PUSH, POP, NOP ); -- pragma CLOCK ck -- pragma CURRENT_STATE CURRENT_STATE -- pragma NEXT_STATE NEXT_STATE -- pragma RETURN_STATE RETURN_STATE -- pragma CONTROL CTRL -- pragma PUSH PUSH -- pragma POP POP -- pragma NOP NOP -- pragma SCAN_TEST t_mode -- pragma SCAN_IN s_in -- pragma SCAN_OUT s_out SIGNAL CURRENT_STATE, NEXT_STATE, RETURN_STATE : STATE_TYPE; SIGNAL CTRL : CONTROL; SIGNAL STACK_0, STACK_1 : STATE_TYPE ; BEGIN PROCESS ( CURRENT_STATE, I, reset ) BEGIN IF ( reset ) THEN NEXT_STATE <= S0; o <= '0' ; ELSE CASE CURRENT_STATE IS WHEN S0 => NEXT_STATE <= S1; RETURN_STATE <= S5; CTRL <= PUSH; o <= '0'; WHEN S1 => IF ( I = '1' ) THEN NEXT_STATE <= S2; CTRL <= NOP; ELSE NEXT_STATE <= S3; CTRL <= NOP; END IF; o <= '0'; WHEN S2 => NEXT_STATE <= S4; CTRL <= NOP; o <= '0'; WHEN S3 => NEXT_STATE <= S4; CTRL <= NOP; o <= '0'; WHEN S4 => NEXT_STATE <= STACK_0; CTRL <= POP; o <= '1'; WHEN S5 => IF ( I = '1' ) THEN NEXT_STATE <= S1; RETURN_STATE <= S0 ; CTRL <= PUSH; ELSE NEXT_STATE <= S5; CTRL <= NOP; END IF ; o <= '0'; WHEN others => ASSERT ( '1' ) REPORT "Illegal state"; END CASE; END IF ; END PROCESS; PROCESS ( ck ) BEGIN IF ( ck = '0' AND NOT ck'STABLE ) THEN CURRENT_STATE <= NEXT_STATE; CASE CTRL IS WHEN POP => STACK_0 <= STACK_1; WHEN PUSH => STACK_1 <= STACK_0; STACK_0 <= RETURN_STATE; WHEN NOP => NULL; END CASE; END IF; END PROCESS; END auto;
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