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Name

proof - Formal proof between two behavioural descriptions

Origin

This software belongs to the ALLIANCE CAD system from the CAO-VLSI team at ASIM/LIP6/UPMC laboratory.
LIP6/ASIM
University P. et M. Curie 4, place Jussieu 75252 PARIS Cedex 05 FRANCE
Fax : {33/0} 1.44.27.62.86
E-mail support : alliance-support@asim.lip6.fr

Synopsis

proof [-a] [-d] file1 file2

Description

Made to run on a data-flow description, proof supports the same subset of VHDL as asimut and bop and scmap (for further informations about this subset, please call the VHDL manual). proof uses a Reduced Ordered Binary Decision Diagrams representation that permits the designer to prove easily the functionnal equivalence between two behavioral descriptions. proof is generally used in order to compare a behavioural specification with an extracted behaviour obtained by yagle.
In default mode, a collapsing phase is done on the description by removing all the auxiliary signals (the BDD of the outputs, the registers and the buses are described from the inputs or the registers). The two descriptions must contain the same ressources (signals register with the same name). It is possible to use the .inf file in yagle to rename the registers in the extracted behavioural description (see man yagle). The datas and the commands (the guarded expressions) must match separatly. The buses corresponding to completely specified logical functions are represented by a logical multiplexor in both descriptions. The two descriptions must have the same interface (VHDL entity), if they do not, the formal proof is stopped.
proof only uses two system environment variables related to the work directory.

Environment Variables

MBK_WORK_LIB gives the path for the behavioral descriptions. The default value is the current directory.

MBK_CATA_LIB gives some auxiliary pathes for the behavioral descriptions. The default value is the current directory.

Options

Options may be given in any order before the filenames.

-a
This option asks proof to keep the common auxiliary signals. proof keeps all intermediate signals that have the same name in both descriptions (A common signal is considered as an input and an output of each description). This option can be useful for descriptions containing large equations. It may be used when proof has failed or if you want to debug in step by step mode the two different descriptions.
-d
The program displays errors when the behavioral descriptions are different. Equations are displayed when it's possible.

Example

proof -a -d adder1 adder2

See Also

bop (1), glop (1), scmap (1), c4map (1), asimut(1) , vhdl(5) , yagle(1) , vbe(5) .

Bug Report

This tool is under development at the ASIM/LIP6/UPMC laboratory, cao-vlsi research team.
We need your feedbak to improve documentation and tools. If you find bugs, please fill-in the form at http://asim.lip6.fr/alliance/support/bug-report/ Thanks for doing this.


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