ALLIANCE VHDL Subset
This software belongs to the ALLIANCE CAD system from the CAO-VLSI team at
ASIM/LIP6/UPMC laboratory.
LIP6/ASIM
University P. et M. Curie
4, place Jussieu
75252 PARIS Cedex 05
FRANCE
Fax : {33/0} 1.44.27.62.86
E-mail support : alliance-support@asim.lip6.fr
The ALLIANCE VHDL subset is dedicated to digital synchronous circuits
design. The same subset is used for:
logic simulation (asimut)
logic synthesis (bop, scmap, glop)
functionnal abstraction (yagle)
formal proof (proof)
The ALLIANCE VHDL subset is fully compatible with the IEEE VHDL standard Ref. 1076 (1987). That means that a VHDL description using the ALLIANCE subset can be simulated with any full-VHDL commercial compiler-simulator.
Here follows the main restrictions of the ALLIANCE subset.
The VHDL description of a circuit is made of two seperate parts: the external view and the internal view.
The external view defines the name of the circuit and its interface. The interface of a circuit is a list of ports. Each port is specified by its name, its mode, its type, its constraint for an array and, its kind.
The mode of a port depends only on the manner the port is used inside the circuit (in the internal view of the circuit). If the value of a port is to be read in the view of the description, the port must be declared with the mode in. If the value of a port is to be written by the internal view, the port must be declared with the mode out. If both above conditions are satisfied the port must be declared with the mode inout.
Only structural and behavioural data flow are supported as internal view.
In order to allow automatic translation from structural VHDL to other
netlist formats (EDIF, ALLIANCE, COMPASS, ...) it is not possible to mix
behavioural and structural description. Of course, a circuit, a subcircuit
or a cell can have two different descriptions:
a structural view may be defined in a file with a .vst extension
(see vst(5)
).
a behavioural data flow description may be defined in a file with a
.vbe extension (see vbe(5)
).
A typical VHDL model will be made of a hierarcical structural description (a hierarchy of structural files) and, for each leaf cell, a behavioural description.
In a behavioural description, only concurrent statements (except process) are supported. Up to now, sequential statements are not allowed by the ALLIANCE VHDL compiler.
As behavioural descriptions are used for both logic simulation and logic synthesis, detailed timing information is not needed. That means, within a concurrent statement no delay can be specified (after is not supported).
A predefined set of types has been defined (other user defined types are not supported):
In the next ALLIANCE release the VHDL subset will be largely extended (sequential statements, user defined types) .
vst(5) , vbe(5) , asimut(1) , bop(1) , glop(1) , scmap(1) , c4map(1) , proof(1) , yagle(1)
This tool is under development at the ASIM/LIP6/UPMC laboratory, cao-vlsi
research team.
We need your feedbak to improve documentation and tools.
If you find bugs, please fill-in the form at
http://asim.lip6.fr/alliance/support/bug-report/
Thanks for doing this.