asimut
)
bop
, scmap
, glop
)
yagle
)
proof
)
The ALLIANCE VHDL subset is fully compatible with the IEEE VHDL standard Ref. 1076 (1987). That means that a VHDL description using the ALLIANCE subset can be simulated with any full-VHDL commercial compiler-simulator.
Here follows the main restrictions of the ALLIANCE subset.
The VHDL description of a circuit is made of two seperate parts: the external view and the internal view.
The external view defines the name of the circuit and its interface. The interface of a circuit is a list of ports. Each port is specified by its name, its mode, its type, its constraint for an array and, its kind.
The mode of a port depends only on the manner the port is
used inside the circuit (in the internal view of the circuit).
If the value of a port is to be read in the view of
the description, the port must be declared with the mode
IN
. If the value of a port is to be written by the
internal view, the port must be declared with the mode
OUT
. If both above conditions are satisfied
the port must be declared with the mode INOUT
.
Only structural and behavioural data flow are supported as internal view.
In order to allow automatic translation from structural VHDL to other netlist formats (EDIF, ALLIANCE, COMPASS, ...) it is not possible to mix behavioural and structural description. Of course, a circuit, a subcircuit or a cell can have two different descriptions:
.vst
extension (see vst).
.vbe
extension
(see vbe).
A typical VHDL model will be made of a hierarchical structural description (a hierarchy of structural files) and, for each leaf cell, a behavioural description.
In a behavioural description, only concurrent statements
(except PROCESS
) are supported. Up to now, sequential
statements are not allowed by the ALLIANCE VHDL compiler.
As behavioural descriptions are used for both logic simulation
and logic synthesis, detailed timing information is
not needed. That means, within a concurrent statement no
delay can be specified (AFTER
is not supported).
A predefined set of types has been defined (other user defined types are not supported):
BIT
|
the predefined standard bit type ('0' or '1') |
BIT_VECTOR
|
array of bits |
MUX_BIT
|
a resolved subtype of BIT using the
mux resolution function. This function
checks that only one driver is actually connected
to a signal. The effective value of the
signal is the value of the active driver.
If all drivers are disconnected, the value
of the signal is '1' (pull up). A signal of
type MUX_BIT must be declared with the kind
BUS .
|
MUX_VECTOR
|
array of MUX_BIT
|
WOR_BIT
|
a resolved subtype of BIT using the
wor resolution function. This function
allows a signal be driven by more than one driver.
All active drivers have to drive the same
value. The effective value of the signal is
the value of active drivers. If all drivers
are disconnected, the value of the signal
is '1' (pull up). A signal of type WOR_BIT
must be declared with the kind BUS .
|
WOR_VECTOR
|
array of WOR_BIT
|
REG_BIT
|
a resolved subtype of BIT using
the reg resolution function. This
function checks that only one driver is actually
connected to a signal. The effective value of the
signal is the value of the active driver. A
signal of type REG_BIT must be declared
with the kind REGISTER (which makes the
signal keep its previous value when all
drivers are disconnected).
|
REG_VECTOR
|
array of REG_BIT
|
In the next ALLIANCE release the VHDL subset will be largely extended (sequential statements, user defined types).
![]() Université Pierre et Marie Curie - CNRS |
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