Hi David, On Tue, Feb 26, 2002 at 02:36:27PM -0800, David Elmore wrote: > Alliance, > We are using the Alliance tool suite in our latest VLSI > chip design. In addition, in the past we have used the ActiveHDL VHDL > development tool and simulator for the development of FPGA code and have > > learned to like their simulator. What we would like to do is to develop > VHDL code using the Alliance tool and simulate it on the Aldec tool. We > realize Alliance provides a simlulator, however, we like the graphical > nature of the Aldec tool. We have run into two problems with this > approach, as I describe below: > 1) Data Types: The Alliance tool uses data types that are not recognized > > by the ActiveHDL compiler, such as bit vectors and reg vectors. The > Aldec tool requires a resolution function in order to recognize these > outside-the-standard data types. Can you help me locate a resolution > function for these data types? yes, you will find this package attached to this mail. > 2) Linkages: When generating structural code, the Alliance tool uses > linkages. As I understand it, linkages are used in VHDL '87 but not in > VHDL '93. The Aldec tool was developed for VHDL '93. Can you recommend > an approach for getting around this problem ? We use linkage in structural descriptions extracted by lynx because we don't known the orientation of cell ports during the netlist extraction process. May be someone on the Alliance mailling list knows how to resolve this problem. From my point of view you have to write a script that replace "linkage" by "in", "out" or "inout" according to the behavioral description of each leaf cells. > > Thank you for you help with this. > > -- > David Elmore > The MicroDisplay Corporation > 3055 Research Drive > San Pablo, Calif. 94806 > Phone: (510)-243-9515 x115 > FAX: (510)-243-9522 Regards, (_) ___ Ludovic JACOMME _ _ ( ) ( ) ( ) ( 6 ) Laboratoire LIP6, Equipe ASIM ( ) (_) ( _ ) Couloir 65-66, 4eme etage Porte 405, ( )___ ( ) Universite P. et M. Curie (P6) (_____) (_) 4 place Jussieu, 75252 Paris Cedex 05 Tel: (33) 01.44.27.27.06 01.44.27.54.15 Fax: (33) 01.44.27.72.80 ICQ: 62526530 mailto: Ludovic.Jacomme@asim.lip6.fr http: //www-asim.lip6.fr/~ludo
-- -- Package of the MASI Laboratory, -- University Pierre and Marie CURIE, Paris 6 -- Author : VUONG Huu Nghia -- Date : 15 Nov 94 -- -- This package contains the various resolution function implemented -- in ASIMUT, and allows the simulation on standard VHDL simulator. -- Package p6b_pkg is function REG ( X : bit_vector ) return bit; subtype reg_bit is REG bit; type reg_vector is array ( natural range <>) of reg_bit; TYPE mux_ubit IS ( 'X', -- Forcing Unknown '0', -- Forcing 0 '1', -- Forcing 1 'Z' -- High Impedance ); type mux_uvector is ARRAY (natural range <>) of mux_ubit; function MUX ( m : mux_uvector ) return mux_ubit; subtype mux_bit is MUX mux_ubit; type mux_vector is array ( natural range <>) of mux_bit; function WOR ( X : bit_vector ) return bit; subtype wor_bit is WOR bit; type wor_vector is array ( natural range <>) of wor_bit; function TO_BIT_VECTOR (m : mux_vector) return bit_vector; function to_reg_bit (m : mux_bit ) return reg_bit; function to_reg_vector (m : mux_vector) return reg_vector; function to_reg_vector (m : bit_vector) return reg_vector; function to_mux_bit (m : bit ) return mux_bit; function to_bit_vector (m : reg_vector) return bit_vector; function to_mux_vector (x : bit_vector) return mux_vector; function to_mux_vector (m : reg_vector) return mux_vector; function bitoreg (m :reg_bit) return bit; function "+"(LEFT:reg_vector; RIGHT:bit) return reg_vector; End p6b_pkg; library P6B_LIB; Package body p6b_pkg is function REG ( X: bit_vector ) return bit is variable Res : bit; begin if X'length = 1 then return X(X'high); else assert (false) report "Conflicts" severity WARNING; return '0'; end if; end REG; function WOR( X : bit_vector ) return bit is variable Res : bit; begin if X'length = 0 then return '1'; elsif X'length = 1 then return X(X'high); else Res := X(X'high); for i in X'low to X'high loop assert ( X(I) = Res ) report "Conflicts" severity WARNING; end loop; return Res; end if; end WOR; function TO_BIT_VECTOR (m : mux_vector ) return bit_vector is alias sm : mux_vector (m'LENGTH-1 downto 0) is m; variable result : bit_vector (m'LENGTH-1 downto 0) ; begin for i in result'RANGE loop case sm(i) is when '0' => result(i) := '0'; when '1'=> result(i) := '1'; when others =>result(i) := '1'; end case; end loop; return result; end TO_BIT_VECTOR; function to_reg_bit(m : mux_bit) return reg_bit is alias sm : mux_bit is m; variable result : reg_bit; begin case sm is when '0' => result:= '0'; when '1' => result:= '1'; when others => result := '1'; end case; return result; end; function to_bit_vector (m : reg_vector ) return bit_vector is ALIAS sm : reg_vector (1 to m'LENGTH) is m; VARIABLE result : bit_vector (1 to m'LENGTH) ; begin for i in result'RANGE loop case sm(i) is when '0' => result(i) := '0'; when '1'=> result(i) := '1'; end case; end loop; return result; end; function to_reg_vector (m : mux_vector ) return reg_vector is ALIAS sm : mux_vector (m'LENGTH-1 downto 0) is m; VARIABLE result : reg_vector (m'LENGTH-1 downto 0) ; begin for i in result'RANGE loop case sm(i) is when '0' => result(i) := '0'; when '1'=> result(i) := '1'; when others =>result(i):='1'; end case; end loop; return result; end; function to_mux_bit(m: bit) return mux_bit is alias sm : bit is m; variable result : mux_bit ; begin case m is when '0' =>result := '0'; when '1' =>result := '1'; end case; return result; end; function to_reg_vector (m : bit_vector ) return reg_vector is ALIAS sm : bit_vector (m'LENGTH-1 downto 0) is m; VARIABLE result : reg_vector (m'LENGTH-1 downto 0) ; begin for i in result'RANGE loop case sm(i) is when '0' => result(i) := '0'; when '1'=> result(i) := '1'; end case; end loop; return result; end; function bitoreg (m : reg_bit ) return bit is ALIAS sm : reg_bit is m; VARIABLE result : bit ; begin case sm is when '0' => result := '0'; when '1'=> result := '1'; end case; return result; end; function to_mux_vector (m : reg_vector ) return mux_vector is ALIAS sm : reg_vector (m'LENGTH-1 downto 0) is m; VARIABLE result : mux_vector (m'LENGTH-1 downto 0) ; begin for i in result'RANGE loop case sm(i) is when '0' => result(i) := '0'; when '1'=> result(i) := '1'; end case; end loop; return result; end; function to_mux_vector (x : bit_vector ) return mux_vector is ALIAS sm : bit_vector (x'LENGTH-1 downto 0) is x; VARIABLE result : mux_vector (x'LENGTH-1 downto 0) ; begin for i in result'RANGE loop case sm(i) is when '0' => result(i) := '0'; when '1'=> result(i) := '1'; end case; end loop; return result; end; function "+" (LEFT: reg_vector; RIGHT: bit) return reg_vector is variable RESULT: reg_vector(left'length-1 downto 0); begin result := left; if not right='1' then return result; end if; for I in RESULT'reverse_range loop result(i) := not left(i); exit when result(i)='1'; end loop; return RESULT; end; TYPE mux_table IS ARRAY(mux_ubit,mux_ubit) OF mux_ubit; CONSTANT resolution_table : mux_table := ( -- --------------------------------------------------------- -- | X 0 1 Z | | -- --------------------------------------------------------- ( 'X', 'X', 'X', 'X'), -- | X | ( 'X', '0', 'X', '0'), -- | 0 | ( 'X', 'X', '1', '1'), -- | 1 | ( 'X', '0', '1', 'Z') -- | Z | ); FUNCTION MUX ( m : mux_uvector ) RETURN mux_ubit IS VARIABLE result : mux_ubit := 'Z'; --etat par defaut BEGIN IF (m'LENGTH = 0) THEN RETURN result; elsif(m'length = 1 ) then return m(m'high); else FOR i IN m'RANGE LOOP result :=resolution_table (result,m(i)); END LOOP; END IF; RETURN result; END MUX; end p6b_pkg;