.vbe
and in a
.c
file: The behavioural description addaccu.vbe
is
used for simulation purposes as a proof-of-concept and to prove that the
resulting layout satisfies the specifications; the core.c
and
addaccu.c
files describe the core and the chip structure respectively.
What this means is that there is no need to use a cells' mapper since the fitting
is already done in the structural description (.c
files).
By comparing the core.c
and addaccu.vbe
, you will find
that the former describes the core's through a set of C function calls
while the latter gives its functional description.
Also, you will notice that the core.c
file directly instantiates the
required standard cells in order to generate the VHDL structural description
(core.vst
).
addaccu.c
is provided to generate the full chip's description
(addaccu.vst
). Notice that this file declares all of the chip's
connectors and not just those given in the core.c
file. Since this
file describes the full chip structure, it instatiates all of the necessary pads.
Makefile
you will have an automatic replay of the
addaccu
tutorial. However you will be doing the whole chip design
and verification at once.
To get a more detailed insigth of the methodology you could still use the
Makefile
but now with other targets, not just with the primary one.
The following table is provided as a hint:
Target | Action | Results |
---|---|---|
clean | clean up the directory for tutorial re-run | Minimum required files |
specifications.pat | check the correctness of specifications (Data-FLow VHDL) running the logic simulation. |
specifications.pat
|
core.vst |
generate the structural description of the circuit's core using the genlib
language. core.c is the schematic capture of the core.
|
core.vst
|
addaccu.vst |
generate the structural description of the complete circuit using the genlib
language. addaccu.c is the schematic capture of the circuit.The circuit can be generated only if the core is generated. |
addaccu.vst
|
schema.pat | check the correctness of the generated structural description running the logic simulation. |
schema.pat
|
core.ap | place and route the circuit's core. |
core.ap
|
core.al | extract netlist from symbolic layout for the core. |
core.al
|
core.lvx | compare extracted netlist and structural description to check that the standard cell router performed correctly. |
core.lvx
|
result.pat | simulate the extracted netlist for cross checking. |
result.pat
|
addaccu.ap |
place and route the circuit (core and pads). This can be done only if the extracted netlist is correct. |
addaccu.ap
|
graal | look at the circuit under graal. | - |
addaccu.al | extract netlist from symbolic layout for the circuit. |
addaccu.al
|
addaccu.lvx | compare extracted netlist and structural description to check that the ring router performed correctly. |
addaccu.lvx
|
extracted.pat | simulate the extracted netlist. |
extracted.pat
|
addaccue.vbe | generate a Data-Flow description from the transistor level extracted netlist. |
addaccue.al addaccu.rep addaccu.vbe
|
abstracted.pat | simulate the extracted data flow description. |
abstracted.pat
|
addaccu.proof | check the correctness of the extracted data flow description running the formal prover. |
addaccu.proof
|
addaccu.drc | check design rules |
addaccu.drc addaccu_drc.cif addaccu_rng.cif
|
addaccu.cif | generates CIF description for 1.0 um process. |
addaccu.cif
|
dreal | look at the circuit under dreal. | - |