alliance-support '1998
Re: On supporting


Czo [Olivier SIROL] (Olivier.Sirol@asim.lip6.fr)
Tue, 10 Feb 1998 11:00:13 +0100

YunSeok, Cho wrote: (1) The "vbe" manual wrotes that no sequential statement are supported. Most of VHDL-related materals use sequential statement (PROCESS). So we must change the VHDL code for simulation. Please let me know why sequential statements are missing. We want the same VHDL subset for simulation and synthezis Allowing PROCESS in our VHDL subset is a very hard task This VHDL subset is Register Transfer Level, this means we describe netlists knowing about each register (it's not the case when using PROCESS). The way to achive an FSM whithin Alliance is to use "syf" wich will generate a VBE file from an FSM description (wich is rather near PROCESS of full VHDL) Also, I wonder if the "alliance" software supports "PROCESS" statement in the near future. No, not in the near future. (2) An error message in using "fpmap" : But .xnf file is not generated. The messages reported on the screen are: I am forwarding this question to the maintainer of fpmap. -- Sincerely, Olivier. ==================================================================== Olivier SIROL Alliance Team ASIM/LIP6/UPMC Coul. 55-65, 2e etg, Bur. 213 75252 Paris Cedex 05 mailto:Olivier.Sirol@lip6.fr Tel: (33/0) 1.44.27.30.43 http://asim.lip6.fr/~czo/ Fax: (33/0) 1.44.27.72.80 ===================== Alliance on the WWW ========================== - Home page : http://asim.lip6.fr/alliance/ - Ftp site : ftp://asim.lip6.fr/pub/alliance/ - E-mail support : mailto:alliance-support@asim.lip6.fr ====================================================================

 



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