Hello dear Mr Onodera, > >From the "man page" of "ring", "ring" needs two files;an input netlist > and a parameter file. > It seems OK for us to create the parameter file, but we meet > difficulties to create the input netlist file. > In the symbolic pad library, we found the following pads: > > pck_sp po_sp pvdde_sp pvsse_sp > pi_sp pot_sp pvddeck_sp pvsseck_sp > piot_sp potw_sp pvddi_sp pvssi_sp > piotw_sp pow_sp pvddick_sp pvssick_sp > > The function of some pads, such as pi_sp and po_sp, seem to be trivial. > However, the function of other pads are not clear to us. To each of these pad is assiated a `vbe' description that specifies its behaviour, but that's not necessarilly very clear, so let me give you a few hints : pi_sp : input pad po_sp : ouptut pad pow_sp : weak output pad, ie for small loads on the PCB pot_sp : tri-state output pad potw_sp : weak tri-state output pad piot_sp : tri-state bi-directional pad piotw_sp : weak version of piot_sp pvdde_sp : external power supply, ie power supply for the pads' amplifiers pvsse_sp : external ground, ie ground for the pads' amplifiers pvddi_sp : internal power supplies, ie power supply for the core logic pvssi_sp : ground for the core logic The pads amplifiers require a large amount of current, and to avoid noise on the logic signals in the circuit when an output (or a very loaded input) changes, there are two separate supplies. pck_sp : clock input pad. The clock feeding a circuit must be connected to this pad, and as you may notice, this pad has no output on its south face. In fact, `clock lines' are spread around the circuit, and amplified using the buffers of the p[vdd,vss][i,e]ck_sp pads. pvddeck_sp: same as above, but also containing a clock amplifier pvsseck_sp: same as above, but also containing a clock amplifier pvddick_sp: same as above, but also containing a clock amplifier pvssick_sp: same as above, but also containing a clock amplifier There is a small and IMHO not very well written technical report that gives more explanation on that. I put it on our ftp : cao-vlsi.ibp.fr, /pub/alliance/pads.ps.gz Thanks for your support, Fred > Maintenant, le coeur du problème : il nous faut concevoir un circuit > d'essai qui n'a pas d'horloge et qui réagira de façon asynchrone sur des > fronts montants et descendants de différents signaux d'entrées. En quoi > les pads risquent de poser problème? Afin de faire taire la bete, il faut (je ne vois pas d'autres solutions) mettre un plot «~pck_sp~» et lui coller un niveau style vdd de l'exterieur. Ainsi tout le monde est content: y'a plus de signaux flottant, et y'a pas d'horloge non plus. Le cout est un pad et une pinoche a relier a vdd. > Comment faire pour concevoir un circuit sans horloge? Ça, c'est hors de ma juridiction! Fred, Former Alliance Consulting Inc -- @----------------------,-,-----,-------------------------------------@ |Ad augusta Frederic PETROT: MC d'ASIM/LIP6/UPMC (Paris VI) | |Per angusta 55-65/201 4 place Jussieu, 75252 Paris Cedex 05 | |Work:331 44275415 Fax:331 44276286 Frederic.Petrot@lip6.fr | |Home:331 47129513 Pager:336 56278636 //asim.lip6.fr/~fred/ | @--------------------------------------------------------------------@