Alliance is a complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools. A complete set of portable CMOS libraries is provided, including a RAM generator, a ROM generator and a data-path compiler. Alliance is the result of a ten year effort spent at ASIM laboratory of the Pierre et Marie Curie University (Paris VI, France). Alliance has been used for research projects such as the 875 000 transistors StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL Router.

 

 

Process independence : The main target is digital design. The process independence relies on a symbolic layout approach and a fully automatic process mapping from a silicon supplier to another. The existing portable libraries are designed for standard CMOS process with one poly and two metals. New high performance library is being designed.

Software portability : The Alliance package has been designed to run on low-cost workstations based on PCs under Linux for teaching purposes, but can take advantage of the huge memory capacity of nowadays Unix supercomputers for advanced research projects. Most programs can be used on a dumb text terminal. Graphical ones require XWindow X11/Motif user interface. Port is being done on Hp-Ux, FreeBSD and Windows NT using LessTiff as a Motif replacement.

Modularity : Each tool can operate as a standalone program, and is interfaced to standard external formats such as EDIF, VHDL, SPICE CIF or GDSII . You can, for example, use only the VHDL compiler simulator, or the functional abstractor. Easiness and simplicity have been preferred to sophisticated approaches. Both on-line Unix manuals and paper documentation are available with each tool.

Interoperability : Thanks to the standard formats used for the external files, Alliance is an open software. You can use most of the Alliance tools with other VLSI frameworks such as CADENCE. The Alliance toolset support a zero-default top-down design flow with not only construction tools (layout editor, logic synthesis, automatic place and route) but also validation tools, from design rule checker to functional abstractor and static timing analysis.

Library portability : A given foundry may provide new CMOS processes each year. The difficulty is even higher when multisourcing is to be achieved. In order to preserve the investment in cell library design, it is necessary to ensure that it can be used on different target technologies. Alliance will provide you with more than 600 cells, either standard cells or parameterized layout generator leaf cells. All the cells are provided with all necessary views: physical layout, transistor level schematic, and VHDL model.

Parameterized generators : The generators are designed by abutment, using a tiler and leaf-cell approach. The area lost by using symbolic layout compared to micron design is estimated ranging from 10% to 20%. Six optimized block generators are currently available in Alliance. They all output a symbolic layout, a VHDL behavior, a set of patterns for test purpose, a netlist, an icon, and a datasheet indicating size and timing estimation for a given technology.

 



Alliance Web Site © 1997, 2002 ASIM/LIP6/UPMC, page maintained by Czo [Olivier Sirol] , last updated on 05 June 2001.