alliance-support '1999
BUG glop  : fanout max negatif


dea9194@enseig.lip6.fr
Fri, 5 Nov 1999 12:04:46 +0100

Begin Alliance bug report 1.3 ------------------------------------------------------------------- Posted on : 1999 November 05 (Friday at 12:04) MET by : dea9194@enseig.lip6.fr subject : BUG glop  : fanout max negatif version : Alliance 3.5.9 ------------------------------------------------------------------- Problem description : --------------------- En utilisant glop avec l'option -i on obtient la reponse suivante : INSTANCE : excp_0 [oa22_x2] Fanout max = -1494967 Sum Cin = 32, 1 gate driven la ligne de commande etait glop -i mips_seqo mips_seqo mips_seqo_scmap cette erreur apparait aussi bien sous linux que sous station Environnement : --------------- Platform : glop -i mips_seqo mips_seqo mips_seqo_scmap MBK_CATA_LIB=.:/users/soft5/newlabo/alliance/archi/SunOS/cells/sxlib:/users/soft5/newlabo/alliance/archi/SunOS/cells/padlib MBK_IN_LO=vst MBK_OUT_LO=vst MBK_VDD=vdd MBK_VSS=vss MBK_WORK_LIB=. How to reproduce the bug : -------------------------- mips_seqo_scmap.lax : ## fichier lax pour l'automate du Mips ##Parametre s d'optimisation pour bop ## type d'optimisation: ## 0 optimisation en surface, ## 4 optimisation en delais #M{2} ##Niveau d'optimisation: #L{2} ## Fanout factor : the max fanout of the ## output connector is multiplied by this factor #T{4000} ## Buffered Input : this is a list of primary inputs whith ## the number of buffer you want to add. #B{ reset:4; frz:4; } ## Output Capacitance : The primary outputs of the circuit ## can have capacitance. (in fF) #C{ ctlopx(8):700; ctlopx(7):700; ctlopx(6):700; ctlopx(5):700; ctlopx(4):700; ctlopx(3):700; ctlopx(2):700; ctlopx(1):700; ctlopx(0):700; ctlopy(6)% 3A700; ctlopy(5):700; ctlopy(4):700; ctlopy(3):700; ctlopy(2):700; ctlopy(1):700; ctlopy(0):700; wenable(10):700; wenable(9):700; wenable(8):700; wenable(7):700; wenable(6):700; wenable(5):700; wenable(4):700; wenable(3):700; wenable(2):700; wenable(1):700; wenable(0):700; } mips_seqo.vst -- VHDL structural description generated from `mips_seqo` -- date : Fri Nov 5 11:29:23 1999 -- Entity Declaration ENTITY mips_seqo IS PORT ( ck : in BIT; -- ck frz : in BIT; -- frz rqs : in BIT; -- rqs reset : in BIT; -- reset resnu l : in BIT; -- resnul alu_sign : in BIT; -- alu_sign ir_opcod : in BIT_VECTOR (18 DOWNTO 0); -- ir_opcod vdd : in BIT; -- vdd vss : in BIT; -- vss scin : in BIT; -- scin test : in BIT; -- test itrqs : in BIT; -- itrqs adrs : in BIT_VECTOR (1 DOWNTO 0); -- adrs exrqs : in BIT; -- exrqs ctlopx : out BIT_VECTOR (8 DOWNTO 0); -- ctlopx ctlopy : out BIT_VECTOR (6 DOWNTO 0); -- ctlopy ctlalu : out BIT_VECTOR (5 DOWNTO 0); -- ctlalu wenable : out BIT_VECTOR (10 DOWNTO 0); -- wenable ctlrw : out BIT_VECTOR (4 DOWNTO 0); -- ctlrw ctladr : out BIT; -- ctladr excp : out BIT_VECTOR (6 DOWNTO 0); -- excp scout : inout BIT -- scout ); END mips_seqo; -- Architecture Declaration ARCHITECTURE VST OF mi ps_seqo IS COMPONENT oa2a2a2a24_x2 port ( i0 : in BIT; -- i0 i1 : in BIT; -- i1 i2 : in BIT; -- i2 i3 : in BIT; -- i3 i4 : in BIT; -- i4 i5 : in BIT; -- i5 i6 : in BIT; -- i6 i7 : in BIT; -- i7 q : out BIT; -- q vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT noa2a2a2a24_x1 port ( i0 : in BIT; -- i0 i1 : in BIT; -- i1 i2 : in BIT; -- i2 i3 : in BIT; -- i3 i4 : in BIT; -- i4 i5 : in BIT; -- i5 i6 : in BIT; -- i6 i7 : in BIT; -- i7 nq : out BIT; -- nq vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT a4_x2 port %2 8 i0 : in BIT; -- i0 i1 : in BIT; -- i1 i2 : in BIT; -- i2 i3 : in BIT; -- i3 q : out BIT; -- q vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT o4_x2 port ( i0 : in BIT; -- i0 i1 : in BIT; -- i1 i2 : in BIT; -- i2 i3 : in BIT; -- i3 q : out BIT; -- q vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT oa2a22_x2 port ( i0 : in BIT; -- i0 i1 : in BIT; -- i1 i2 : in BIT; -- i2 i3 : in BIT; -- i3 q : out BIT; -- q vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT oa2a2a23_x2 port ( %0 A i0 : in BIT; -- i0 i1 : in BIT; -- i1 i2 : in BIT; -- i2 i3 : in BIT; -- i3 i4 : in BIT; -- i4 i5 : in BIT; -- i5 q : out BIT; -- q vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT on12_x1 port ( i0 : in BIT; -- i0 i1 : in BIT; -- i1 q : out BIT; -- q vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT noa2a2a23_x1 port ( i0 : in BIT; -- i0 i1 : in BIT; -- i1 i2 : in BIT; -- i2 i3 : in BIT; -- i3 i4 : in BIT; -- i4 i5 : in BIT; -- i5 nq : out BIT; -- nq vdd : in BIT; -- vdd vss : in BIT -- vss ); END C OMPONENT; COMPONENT an12_x1 port ( i0 : in BIT; -- i0 i1 : in BIT; -- i1 q : out BIT; -- q vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT no4_x1 port ( i0 : in BIT; -- i0 i1 : in BIT; -- i1 i2 : in BIT; -- i2 i3 : in BIT; -- i3 nq : out BIT; -- nq vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT na3_x1 port ( i0 : in BIT; -- i0 i1 : in BIT; -- i1 i2 : in BIT; -- i2 nq : out BIT; -- nq vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT o3_x2 port ( i0 : in BIT; -- i0 i1 : i n BIT; -- i1 i2 : in BIT; -- i2 q : out BIT; -- q vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT nao22_x1 port ( i0 : in BIT; -- i0 i1 : in BIT; -- i1 i2 : in BIT; -- i2 nq : out BIT; -- nq vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT na4_x1 port ( i0 : in BIT; -- i0 i1 : in BIT; -- i1 i2 : in BIT; -- i2 i3 : in BIT; -- i3 nq : out BIT; -- nq vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT oa22_x2 port ( i0 : in BIT; -- i0 i1 : in BIT; -- i1 i2 : in BIT; -- i2 q : out BIT% 3B -- q vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT ao22_x2 port ( i0 : in BIT; -- i0 i1 : in BIT; -- i1 i2 : in BIT; -- i2 q : out BIT; -- q vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT ao2o22_x2 port ( i0 : in BIT; -- i0 i1 : in BIT; -- i1 i2 : in BIT; -- i2 i3 : in BIT; -- i3 q : out BIT; -- q vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT inv_x1 port ( i : in BIT; -- i nq : out BIT; -- nq vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT noa 22_x1 port ( i0 : in BIT; -- i0 i1 : in BIT; -- i1 i2 : in BIT; -- i2 nq : out BIT; -- nq vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT nao2o22_x1 port ( i0 : in BIT; -- i0 i1 : in BIT; -- i1 i2 : in BIT; -- i2 i3 : in BIT; -- i3 nq : out BIT; -- nq vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT no3_x1 port ( i0 : in BIT; -- i0 i1 : in BIT; -- i1 i2 : in BIT; -- i2 nq : out BIT; -- nq vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT na2_x1 port ( i0 : in BIT; -- i0 i1 % 3A in BIT; -- i1 nq : out BIT; -- nq vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT xr2_x1 port ( i0 : in BIT; -- i0 i1 : in BIT; -- i1 q : out BIT; -- q vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT o2_x2 port ( i0 : in BIT; -- i0 i1 : in BIT; -- i1 q : out BIT; -- q vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT nxr2_x1 port ( i0 : in BIT; -- i0 i1 : in BIT; -- i1 nq : out BIT; -- nq vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT noa2a22_x1 port %2 8 i0 : in BIT; -- i0 i1 : in BIT; -- i1 i2 : in BIT; -- i2 i3 : in BIT; -- i3 nq : out BIT; -- nq vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT a2_x2 port ( i0 : in BIT; -- i0 i1 : in BIT; -- i1 q : out BIT; -- q vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT no2_x1 port ( i0 : in BIT; -- i0 i1 : in BIT; -- i1 nq : out BIT; -- nq vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT a3_x2 port ( i0 : in BIT; -- i0 i1 : in BIT; -- i1 i2 : in BIT; -- i2 q : out BIT; -- q v dd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT sff1_x4 port ( ck : in BIT; -- ck i : in BIT; -- i q : out BIT; -- q vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; SIGNAL aux765_a : BIT; -- aux765_a SIGNAL aux762_a : BIT; -- aux762_a SIGNAL aux758_a : BIT; -- aux758_a SIGNAL aux757_a : BIT; -- aux757_a SIGNAL aux752_a : BIT; -- aux752_a SIGNAL aux742_a : BIT; -- aux742_a SIGNAL aux740_a : BIT; -- aux740_a SIGNAL aux738_a : BIT; -- aux738_a SIGNAL aux737_a : BIT; -- aux737_a SIGNAL aux736_a : BIT; -- aux736_a SIGNAL aux733_a : BIT; -- aux733_a SIGNAL aux732_a : BIT; -- aux732_a SIGNAL aux731_a : BIT; -- aux731_a SIGNAL aux729_a : BIT; -- aux729_a SIGNAL ef_1 : BIT; -- ef_1 SIGNAL aux564_a : BIT; -- aux564_a SIGNAL aux566_a : BIT; -- aux566_a SIGNAL aux567_a : BIT; -- aux567_a SIGNAL aux568_a : BIT; -- aux568_a SIGNAL aux569_a : BIT; -- aux569_a SIGNAL aux570_a : BIT; -- aux570_a SIGNAL aux573_a : BIT; -- aux573_a SIGNAL aux576_a : BIT; -- aux576_a SIGNAL aux577_a : BIT; -- aux577_a SIGNAL aux578_a : BIT; -- aux578_a SIGNAL aux579_a : BIT; -- aux579_a SIGNAL aux580_a : BIT; -- aux580_a SIGNAL aux582_a : BIT; -- aux582_a SIGNAL aux583_a : BIT; -- aux583_a SIGNAL aux587_a : BIT; -- aux587_a SIGNAL aux588_a : BIT; -- aux588_a SIGNAL aux590_a : BIT; -- aux590_a SIGNAL aux591_a : BIT; -- aux591_a SIGNAL aux592_a : BIT; -- aux59 2_a SIGNAL aux595_a : BIT; -- aux595_a SIGNAL aux597_a : BIT; -- aux597_a SIGNAL aux600_a : BIT; -- aux600_a SIGNAL aux601_a : BIT; -- aux601_a SIGNAL aux603_a : BIT; -- aux603_a SIGNAL aux605_a : BIT; -- aux605_a SIGNAL aux609_a : BIT; -- aux609_a SIGNAL aux611_a : BIT; -- aux611_a SIGNAL aux613_a : BIT; -- aux613_a SIGNAL aux615_a : BIT; -- aux615_a SIGNAL aux622_a : BIT; -- aux622_a SIGNAL aux623_a : BIT; -- aux623_a SIGNAL aux626_a : BIT; -- aux626_a SIGNAL aux627_a : BIT; -- aux627_a SIGNAL aux631_a : BIT; -- aux631_a SIGNAL aux633_a : BIT; -- aux633_a SIGNAL aux646_a : BIT; -- aux646_a SIGNAL aux647_a : BIT; -- aux647_a SIGNAL aux648_a : BIT; -- aux648_a SIGNAL aux649_a : BIT; -- aux649_a SIGNAL aux658_a : BIT; -- aux658_a SIGNAL aux659_a : BIT; -- aux659_a SIGNAL aux661_a : BIT; -- aux661_a SIGNAL aux671_a : BIT; -- aux671_a SIGNAL aux672_a : BIT; -- aux672_a SIGNAL aux676_a : BIT; -- aux676_a SIGNAL aux677_a : BIT; -- aux677_a SIGNAL aux681_a : BIT; -- aux681_a SIGNAL aux685_a : BIT; -- aux685_a SIGNAL aux687_a : BIT; -- aux687_a SIGNAL aux696_a : BIT; -- aux696_a SIGNAL aux699_a : BIT; -- aux699_a SIGNAL aux706_a : BIT; -- aux706_a SIGNAL aux712_a : BIT; -- aux712_a SIGNAL aux713_a : BIT; -- aux713_a SIGNAL aux718_a : BIT; -- aux718_a SIGNAL aux720_a : BIT; -- aux720_a SIGNAL aux723_a : BIT; -- aux723_a SIGNAL aux770_a : BIT; -- aux770_a SIGNAL aux775_a : BIT; -- aux775_a SIGNAL auxsc1901 : BIT; -- auxsc1901 S IGNAL auxsc352 : BIT; -- auxsc352 SIGNAL auxsc1865 : BIT; -- auxsc1865 SIGNAL auxsc423 : BIT; -- auxsc423 SIGNAL auxsc50 : BIT; -- auxsc50 SIGNAL auxsc37 : BIT; -- auxsc37 SIGNAL auxsc21 : BIT; -- auxsc21 SIGNAL auxsc92 : BIT; -- auxsc92 SIGNAL auxsc24 : BIT; -- auxsc24 SIGNAL auxsc23 : BIT; -- auxsc23 SIGNAL auxsc1318 : BIT; -- auxsc1318 SIGNAL auxsc105 : BIT; -- auxsc105 SIGNAL auxsc1078 : BIT; -- auxsc1078 SIGNAL auxsc1119 : BIT; -- auxsc1119 SIGNAL auxsc40 : BIT; -- auxsc40 SIGNAL auxsc39 : BIT; -- auxsc39 SIGNAL auxsc1116 : BIT; -- auxsc1116 SIGNAL auxsc278 : BIT; -- auxsc278 SIGNAL auxsc1309 : BIT; -- auxsc1309 SIGNAL auxsc63 : BIT; -- auxsc63 SIGNAL auxsc500 : BIT; -- auxsc500 SIGNAL auxsc1310 : BIT; -- auxsc 1310 SIGNAL auxsc1315 : BIT; -- auxsc1315 SIGNAL auxsc74 : BIT; -- auxsc74 SIGNAL auxsc1317 : BIT; -- auxsc1317 SIGNAL auxsc1319 : BIT; -- auxsc1319 SIGNAL auxsc295 : BIT; -- auxsc295 SIGNAL auxsc20 : BIT; -- auxsc20 SIGNAL auxsc871 : BIT; -- auxsc871 SIGNAL auxsc872 : BIT; -- auxsc872 SIGNAL auxsc877 : BIT; -- auxsc877 SIGNAL auxsc859 : BIT; -- auxsc859 SIGNAL auxsc860 : BIT; -- auxsc860 SIGNAL auxsc46 : BIT; -- auxsc46 SIGNAL auxsc861 : BIT; -- auxsc861 SIGNAL auxsc515 : BIT; -- auxsc515 SIGNAL auxsc862 : BIT; -- auxsc862 SIGNAL auxsc45 : BIT; -- auxsc45 SIGNAL auxsc856 : BIT; -- auxsc856 SIGNAL auxsc47 : BIT; -- auxsc47 SIGNAL auxsc857 : BIT; -- auxsc857 SIGNAL auxsc863 : BIT; -- auxsc863 SIGNAL auxsc864 : BIT ; -- auxsc864 SIGNAL auxsc875 : BIT; -- auxsc875 SIGNAL auxsc482 : BIT; -- auxsc482 SIGNAL auxsc848 : BIT; -- auxsc848 SIGNAL auxsc866 : BIT; -- auxsc866 SIGNAL auxsc830 : BIT; -- auxsc830 SIGNAL auxsc845 : BIT; -- auxsc845 SIGNAL auxsc846 : BIT; -- auxsc846 SIGNAL auxsc847 : BIT; -- auxsc847 SIGNAL auxsc865 : BIT; -- auxsc865 SIGNAL auxsc874 : BIT; -- auxsc874 SIGNAL auxsc878 : BIT; -- auxsc878 SIGNAL auxsc879 : BIT; -- auxsc879 SIGNAL auxsc471 : BIT; -- auxsc471 SIGNAL auxsc472 : BIT; -- auxsc472 SIGNAL auxsc543 : BIT; -- auxsc543 SIGNAL auxsc14 : BIT; -- auxsc14 SIGNAL auxsc703 : BIT; -- auxsc703 SIGNAL auxsc7 : BIT; -- auxsc7 SIGNAL auxsc10 : BIT; -- auxsc10 SIGNAL auxsc6 : BIT; -- auxsc6 SIGNAL auxsc8 : BIT; -- auxsc8 SIGNAL auxsc9 : BIT; -- auxsc9 SIGNAL auxsc956 : BIT; -- auxsc956 SIGNAL auxsc106 : BIT; -- auxsc106 SIGNAL auxsc1320 : BIT; -- auxsc1320 SIGNAL auxsc1322 : BIT; -- auxsc1322 SIGNAL auxsc102 : BIT; -- auxsc102 SIGNAL auxsc27 : BIT; -- auxsc27 SIGNAL auxsc1232 : BIT; -- auxsc1232 SIGNAL auxsc171 : BIT; -- auxsc171 SIGNAL auxsc1636 : BIT; -- auxsc1636 SIGNAL auxsc454 : BIT; -- auxsc454 SIGNAL auxsc455 : BIT; -- auxsc455 SIGNAL auxsc1637 : BIT; -- auxsc1637 SIGNAL auxsc1638 : BIT; -- auxsc1638 SIGNAL auxsc128 : BIT; -- auxsc128 SIGNAL auxsc1541 : BIT; -- auxsc1541 SIGNAL auxsc1632 : BIT; -- auxsc1632 SIGNAL auxsc1642 : BIT; -- auxsc1642 SIGNAL auxsc1643 : BIT; -- auxsc1643 SIGNAL auxsc1639 : BIT; -- auxsc1 639 SIGNAL auxsc1640 : BIT; -- auxsc1640 SIGNAL auxsc1641 : BIT; -- auxsc1641 SIGNAL auxsc1646 : BIT; -- auxsc1646 SIGNAL auxsc1612 : BIT; -- auxsc1612 SIGNAL auxsc1555 : BIT; -- auxsc1555 SIGNAL auxsc1556 : BIT; -- auxsc1556 SIGNAL auxsc1554 : BIT; -- auxsc1554 SIGNAL auxsc1550 : BIT; -- auxsc1550 SIGNAL auxsc1622 : BIT; -- auxsc1622 SIGNAL auxsc1623 : BIT; -- auxsc1623 SIGNAL auxsc1624 : BIT; -- auxsc1624 SIGNAL auxsc1625 : BIT; -- auxsc1625 SIGNAL auxsc213 : BIT; -- auxsc213 SIGNAL auxsc1626 : BIT; -- auxsc1626 SIGNAL auxsc1627 : BIT; -- auxsc1627 SIGNAL auxsc392 : BIT; -- auxsc392 SIGNAL auxsc1628 : BIT; -- auxsc1628 SIGNAL auxsc1629 : BIT; -- auxsc1629 SIGNAL auxsc1621 : BIT; -- auxsc1621 SIGNAL auxsc1630 : BIT; -- a uxsc1630 SIGNAL auxsc1605 : BIT; -- auxsc1605 SIGNAL auxsc690 : BIT; -- auxsc690 SIGNAL auxsc1332 : BIT; -- auxsc1332 SIGNAL auxsc1606 : BIT; -- auxsc1606 SIGNAL auxsc1607 : BIT; -- auxsc1607 SIGNAL auxsc1552 : BIT; -- auxsc1552 SIGNAL auxsc1600 : BIT; -- auxsc1600 SIGNAL auxsc343 : BIT; -- auxsc343 SIGNAL auxsc1567 : BIT; -- auxsc1567 SIGNAL auxsc1568 : BIT; -- auxsc1568 SIGNAL auxsc1570 : BIT; -- auxsc1570 SIGNAL auxsc1573 : BIT; -- auxsc1573 SIGNAL auxsc1601 : BIT; -- auxsc1601 SIGNAL auxsc313 : BIT; -- auxsc313 SIGNAL auxsc1224 : BIT; -- auxsc1224 SIGNAL auxsc1602 : BIT; -- auxsc1602 SIGNAL auxsc1608 : BIT; -- auxsc1608 SIGNAL auxsc1609 : BIT; -- auxsc1609 SIGNAL auxsc1046 : BIT; -- auxsc1046 SIGNAL auxsc1631 : BIT; - - auxsc1631 SIGNAL auxsc1644 : BIT; -- auxsc1644 SIGNAL auxsc1647 : BIT; -- auxsc1647 SIGNAL auxsc1478 : BIT; -- auxsc1478 SIGNAL auxsc1764 : BIT; -- auxsc1764 SIGNAL auxsc1769 : BIT; -- auxsc1769 SIGNAL auxsc1757 : BIT; -- auxsc1757 SIGNAL auxsc1709 : BIT; -- auxsc1709 SIGNAL auxsc1765 : BIT; -- auxsc1765 SIGNAL auxsc1766 : BIT; -- auxsc1766 SIGNAL auxsc1767 : BIT; -- auxsc1767 SIGNAL auxsc1759 : BIT; -- auxsc1759 SIGNAL auxsc1768 : BIT; -- auxsc1768 SIGNAL auxsc1761 : BIT; -- auxsc1761 SIGNAL auxsc1772 : BIT; -- auxsc1772 SIGNAL auxsc1773 : BIT; -- auxsc1773 SIGNAL auxsc1785 : BIT; -- auxsc1785 SIGNAL auxsc1782 : BIT; -- auxsc1782 SIGNAL auxsc1783 : BIT; -- auxsc1783 SIGNAL auxsc1784 : BIT; -- auxsc1784 SIGNAL auxsc1807 : B IT; -- auxsc1807 SIGNAL auxsc1791 : BIT; -- auxsc1791 SIGNAL auxsc1808 : BIT; -- auxsc1808 SIGNAL auxsc1809 : BIT; -- auxsc1809 SIGNAL auxsc1801 : BIT; -- auxsc1801 SIGNAL auxsc1804 : BIT; -- auxsc1804 SIGNAL auxsc1805 : BIT; -- auxsc1805 SIGNAL auxsc1806 : BIT; -- auxsc1806 SIGNAL auxsc1832 : BIT; -- auxsc1832 SIGNAL auxsc1827 : BIT; -- auxsc1827 SIGNAL auxsc1704 : BIT; -- auxsc1704 SIGNAL auxsc1829 : BIT; -- auxsc1829 SIGNAL auxsc1830 : BIT; -- auxsc1830 SIGNAL auxsc1831 : BIT; -- auxsc1831 SIGNAL auxsc1852 : BIT; -- auxsc1852 SIGNAL auxsc1851 : BIT; -- auxsc1851 SIGNAL auxsc1853 : BIT; -- auxsc1853 SIGNAL auxsc1856 : BIT; -- auxsc1856 SIGNAL auxsc1846 : BIT; -- auxsc1846 SIGNAL auxsc1849 : BIT; -- auxsc1849 SIGNAL auxsc1 848 : BIT; -- auxsc1848 SIGNAL auxsc1857 : BIT; -- auxsc1857 SIGNAL auxsc1858 : BIT; -- auxsc1858 SIGNAL auxsc1924 : BIT; -- auxsc1924 SIGNAL auxsc1925 : BIT; -- auxsc1925 SIGNAL auxsc1908 : BIT; -- auxsc1908 SIGNAL auxsc1902 : BIT; -- auxsc1902 SIGNAL auxsc1006 : BIT; -- auxsc1006 SIGNAL auxsc1886 : BIT; -- auxsc1886 SIGNAL auxsc1888 : BIT; -- auxsc1888 SIGNAL auxsc1911 : BIT; -- auxsc1911 SIGNAL auxsc1880 : BIT; -- auxsc1880 SIGNAL auxsc1919 : BIT; -- auxsc1919 SIGNAL auxsc1920 : BIT; -- auxsc1920 SIGNAL auxsc1921 : BIT; -- auxsc1921 SIGNAL auxsc1926 : BIT; -- auxsc1926 SIGNAL auxsc1874 : BIT; -- auxsc1874 SIGNAL auxsc1922 : BIT; -- auxsc1922 SIGNAL auxsc1923 : BIT; -- auxsc1923 SIGNAL auxsc1876 : BIT; -- auxsc1876 SIGN AL auxsc1897 : BIT; -- auxsc1897 SIGNAL auxsc1913 : BIT; -- auxsc1913 SIGNAL auxsc1914 : BIT; -- auxsc1914 SIGNAL auxsc1915 : BIT; -- auxsc1915 SIGNAL auxsc1916 : BIT; -- auxsc1916 SIGNAL auxsc1891 : BIT; -- auxsc1891 SIGNAL auxsc1906 : BIT; -- auxsc1906 SIGNAL auxsc1917 : BIT; -- auxsc1917 SIGNAL auxsc1918 : BIT; -- auxsc1918 SIGNAL auxsc1900 : BIT; -- auxsc1900 SIGNAL auxsc348 : BIT; -- auxsc348 SIGNAL auxsc1939 : BIT; -- auxsc1939 SIGNAL auxsc1940 : BIT; -- auxsc1940 SIGNAL auxsc1941 : BIT; -- auxsc1941 SIGNAL auxsc1942 : BIT; -- auxsc1942 SIGNAL auxsc1943 : BIT; -- auxsc1943 SIGNAL auxsc1944 : BIT; -- auxsc1944 SIGNAL auxsc1945 : BIT; -- auxsc1945 SIGNAL auxsc1946 : BIT; -- auxsc1946 SIGNAL auxsc1947 : BIT; -- auxsc1947 %0 A SIGNAL auxsc1948 : BIT; -- auxsc1948 SIGNAL auxsc1957 : BIT; -- auxsc1957 SIGNAL auxsc1956 : BIT; -- auxsc1956 SIGNAL auxsc1952 : BIT; -- auxsc1952 SIGNAL auxsc1951 : BIT; -- auxsc1951 SIGNAL auxsc1961 : BIT; -- auxsc1961 SIGNAL auxsc1962 : BIT; -- auxsc1962 SIGNAL auxsc645 : BIT; -- auxsc645 SIGNAL auxsc754 : BIT; -- auxsc754 SIGNAL auxsc1967 : BIT; -- auxsc1967 SIGNAL auxsc1969 : BIT; -- auxsc1969 SIGNAL auxsc1970 : BIT; -- auxsc1970 SIGNAL auxsc1974 : BIT; -- auxsc1974 SIGNAL auxsc1975 : BIT; -- auxsc1975 SIGNAL auxsc1973 : BIT; -- auxsc1973 SIGNAL auxsc2023 : BIT; -- auxsc2023 SIGNAL auxsc2024 : BIT; -- auxsc2024 SIGNAL auxsc2025 : BIT; -- auxsc2025 SIGNAL auxsc2036 : BIT; -- auxsc2036 SIGNAL auxsc2037 : BIT; -- auxsc2037 SIGNAL auxsc2038 : BIT; -- auxsc2038 SIGNAL auxsc2014 : BIT; -- auxsc2014 SIGNAL auxsc1999 : BIT; -- auxsc1999 SIGNAL auxsc2039 : BIT; -- auxsc2039 SIGNAL auxsc2040 : BIT; -- auxsc2040 SIGNAL auxsc2041 : BIT; -- auxsc2041 SIGNAL auxsc2042 : BIT; -- auxsc2042 SIGNAL auxsc1255 : BIT; -- auxsc1255 SIGNAL auxsc2015 : BIT; -- auxsc2015 SIGNAL auxsc1982 : BIT; -- auxsc1982 SIGNAL auxsc2034 : BIT; -- auxsc2034 SIGNAL auxsc2016 : BIT; -- auxsc2016 SIGNAL auxsc1981 : BIT; -- auxsc1981 SIGNAL auxsc2043 : BIT; -- auxsc2043 SIGNAL auxsc2020 : BIT; -- auxsc2020 SIGNAL auxsc1732 : BIT; -- auxsc1732 SIGNAL auxsc2017 : BIT; -- auxsc2017 SIGNAL auxsc2021 : BIT; -- auxsc2021 SIGNAL auxsc2029 : BIT; -- auxsc2029 SIGNAL auxsc2044 : BIT; -- auxsc2044 SIGNAL auxsc2011 : BIT; -- auxsc2011 SIGNAL auxsc2076 : BIT; -- auxsc2076 SIGNAL auxsc2071 : BIT; -- auxsc2071 SIGNAL auxsc2077 : BIT; -- auxsc2077 SIGNAL auxsc2067 : BIT; -- auxsc2067 SIGNAL auxsc2068 : BIT; -- auxsc2068 SIGNAL auxsc2073 : BIT; -- auxsc2073 SIGNAL auxsc2078 : BIT; -- auxsc2078 SIGNAL auxsc2079 : BIT; -- auxsc2079 SIGNAL auxsc2080 : BIT; -- auxsc2080 SIGNAL auxsc2070 : BIT; -- auxsc2070 SIGNAL auxsc2072 : BIT; -- auxsc2072 SIGNAL auxsc2075 : BIT; -- auxsc2075 SIGNAL auxsc2081 : BIT; -- auxsc2081 SIGNAL auxsc2065 : BIT; -- auxsc2065 SIGNAL auxsc2091 : BIT; -- auxsc2091 SIGNAL auxsc2095 : BIT; -- auxsc2095 SIGNAL auxsc2085 : BIT; -- auxsc2085 SIGNAL auxsc1028 : BIT; -- auxsc1028 SIGNAL auxsc2092 : BIT ; -- auxsc2092 SIGNAL auxsc425 : BIT; -- auxsc425 SIGNAL auxsc2093 : BIT; -- auxsc2093 SIGNAL auxsc2094 : BIT; -- auxsc2094 SIGNAL auxsc2089 : BIT; -- auxsc2089 SIGNAL auxsc2108 : BIT; -- auxsc2108 SIGNAL auxsc2109 : BIT; -- auxsc2109 SIGNAL auxsc2110 : BIT; -- auxsc2110 SIGNAL auxsc2111 : BIT; -- auxsc2111 SIGNAL auxsc2112 : BIT; -- auxsc2112 SIGNAL auxsc2103 : BIT; -- auxsc2103 SIGNAL auxsc2132 : BIT; -- auxsc2132 SIGNAL auxsc2123 : BIT; -- auxsc2123 SIGNAL auxsc2128 : BIT; -- auxsc2128 SIGNAL auxsc2129 : BIT; -- auxsc2129 SIGNAL auxsc2130 : BIT; -- auxsc2130 SIGNAL auxsc2131 : BIT; -- auxsc2131 SIGNAL auxsc2133 : BIT; -- auxsc2133 SIGNAL auxsc2137 : BIT; -- auxsc2137 SIGNAL auxsc2136 : BIT; -- auxsc2136 SIGNAL auxsc2143 : BIT; -- auxsc2143 SIGNAL auxsc2144 : BIT; -- auxsc2144 SIGNAL auxsc2142 : BIT; -- auxsc2142 SIGNAL auxsc2176 : BIT; -- auxsc2176 SIGNAL auxsc2177 : BIT; -- auxsc2177 SIGNAL auxsc2178 : BIT; -- auxsc2178 SIGNAL auxsc2179 : BIT; -- auxsc2179 SIGNAL auxsc2180 : BIT; -- auxsc2180 SIGNAL auxsc2169 : BIT; -- auxsc2169 SIGNAL auxsc2152 : BIT; -- auxsc2152 SIGNAL auxsc2181 : BIT; -- auxsc2181 SIGNAL auxsc2182 : BIT; -- auxsc2182 SIGNAL auxsc2183 : BIT; -- auxsc2183 SIGNAL auxsc2168 : BIT; -- auxsc2168 SIGNAL auxsc2162 : BIT; -- auxsc2162 SIGNAL auxsc2160 : BIT; -- auxsc2160 SIGNAL auxsc2184 : BIT; -- auxsc2184 SIGNAL auxsc2185 : BIT; -- auxsc2185 SIGNAL auxsc2167 : BIT; -- auxsc2167 SIGNAL auxsc2203 : BIT; -- auxsc2203 SIGNAL a uxsc2204 : BIT; -- auxsc2204 SIGNAL auxsc2200 : BIT; -- auxsc2200 SIGNAL auxsc2201 : BIT; -- auxsc2201 SIGNAL auxsc2206 : BIT; -- auxsc2206 SIGNAL auxsc2207 : BIT; -- auxsc2207 SIGNAL auxsc2237 : BIT; -- auxsc2237 SIGNAL auxsc2241 : BIT; -- auxsc2241 SIGNAL auxsc2242 : BIT; -- auxsc2242 SIGNAL auxsc2243 : BIT; -- auxsc2243 SIGNAL auxsc2265 : BIT; -- auxsc2265 SIGNAL auxsc1261 : BIT; -- auxsc1261 SIGNAL auxsc2266 : BIT; -- auxsc2266 SIGNAL auxsc2253 : BIT; -- auxsc2253 SIGNAL auxsc2254 : BIT; -- auxsc2254 SIGNAL auxsc2246 : BIT; -- auxsc2246 SIGNAL auxsc2238 : BIT; -- auxsc2238 SIGNAL auxsc2247 : BIT; -- auxsc2247 SIGNAL auxsc2248 : BIT; -- auxsc2248 SIGNAL auxsc2255 : BIT; -- auxsc2255 SIGNAL auxsc2210 : BIT; -- auxsc2210 SIGNAL auxsc2244 : BIT; -- auxsc2244 SIGNAL auxsc2256 : BIT; -- auxsc2256 SIGNAL auxsc2257 : BIT; -- auxsc2257 SIGNAL auxsc2258 : BIT; -- auxsc2258 SIGNAL auxsc2259 : BIT; -- auxsc2259 SIGNAL auxsc1651 : BIT; -- auxsc1651 SIGNAL auxsc2260 : BIT; -- auxsc2260 SIGNAL auxsc2261 : BIT; -- auxsc2261 SIGNAL auxsc2262 : BIT; -- auxsc2262 SIGNAL auxsc2263 : BIT; -- auxsc2263 SIGNAL auxsc2264 : BIT; -- auxsc2264 SIGNAL auxsc2267 : BIT; -- auxsc2267 SIGNAL auxsc2286 : BIT; -- auxsc2286 SIGNAL auxsc1270 : BIT; -- auxsc1270 SIGNAL auxsc739 : BIT; -- auxsc739 SIGNAL auxsc2287 : BIT; -- auxsc2287 SIGNAL auxsc2291 : BIT; -- auxsc2291 SIGNAL auxsc2296 : BIT; -- auxsc2296 SIGNAL auxsc2297 : BIT; -- auxsc2297 SIGNAL auxsc2270 : BIT; -- auxsc2270 SIGNAL auxsc2271 : BIT; -- auxsc2271 SIGNAL auxsc2288 : BIT; -- auxsc2288 SIGNAL auxsc2292 : BIT; -- auxsc2292 SIGNAL auxsc2298 : BIT; -- auxsc2298 SIGNAL auxsc2299 : BIT; -- auxsc2299 SIGNAL auxsc2310 : BIT; -- auxsc2310 SIGNAL auxsc2341 : BIT; -- auxsc2341 SIGNAL auxsc2342 : BIT; -- auxsc2342 SIGNAL auxsc2343 : BIT; -- auxsc2343 SIGNAL auxsc2336 : BIT; -- auxsc2336 SIGNAL auxsc2337 : BIT; -- auxsc2337 SIGNAL auxsc2344 : BIT; -- auxsc2344 SIGNAL auxsc2345 : BIT; -- auxsc2345 SIGNAL auxsc2346 : BIT; -- auxsc2346 SIGNAL auxsc2333 : BIT; -- auxsc2333 SIGNAL auxsc2334 : BIT; -- auxsc2334 SIGNAL auxsc2323 : BIT; -- auxsc2323 SIGNAL auxsc2335 : BIT; -- auxsc2335 SIGNAL auxsc2347 : BIT; -- auxsc2347 SIGNAL auxsc2348 : BIT; -- auxsc2348 SIGNAL auxsc2349 : BIT; -- auxsc2349 SIGNAL auxsc2359 : BIT; -- auxsc2359 SIGNAL auxsc2356 : BIT; -- auxsc2356 SIGNAL auxsc2383 : BIT; -- auxsc2383 SIGNAL auxsc2384 : BIT; -- auxsc2384 SIGNAL auxsc2373 : BIT; -- auxsc2373 SIGNAL auxsc2377 : BIT; -- auxsc2377 SIGNAL auxsc728 : BIT; -- auxsc728 SIGNAL auxsc2385 : BIT; -- auxsc2385 SIGNAL auxsc2379 : BIT; -- auxsc2379 SIGNAL auxsc2380 : BIT; -- auxsc2380 SIGNAL auxsc2386 : BIT; -- auxsc2386 SIGNAL auxsc2387 : BIT; -- auxsc2387 SIGNAL auxsc2412 : BIT; -- auxsc2412 SIGNAL auxsc2419 : BIT; -- auxsc2419 SIGNAL auxsc2414 : BIT; -- auxsc2414 SIGNAL auxsc2409 : BIT; -- auxsc2409 SIGNAL auxsc2415 : BIT; -- auxsc2415 SIGNAL auxsc2416 : BIT; -- auxsc2416 SIGNAL auxsc2418 : BIT%3 B -- auxsc2418 SIGNAL auxsc2424 : BIT; -- auxsc2424 SIGNAL auxsc2411 : BIT; -- auxsc2411 SIGNAL auxsc2421 : BIT; -- auxsc2421 SIGNAL auxsc2425 : BIT; -- auxsc2425 SIGNAL auxsc2426 : BIT; -- auxsc2426 SIGNAL auxsc2432 : BIT; -- auxsc2432 SIGNAL auxsc2447 : BIT; -- auxsc2447 SIGNAL auxsc2429 : BIT; -- auxsc2429 SIGNAL auxsc2452 : BIT; -- auxsc2452 SIGNAL auxsc2448 : BIT; -- auxsc2448 SIGNAL auxsc2453 : BIT; -- auxsc2453 SIGNAL auxsc2446 : BIT; -- auxsc2446 SIGNAL auxsc2450 : BIT; -- auxsc2450 SIGNAL auxsc2449 : BIT; -- auxsc2449 SIGNAL auxsc2454 : BIT; -- auxsc2454 SIGNAL auxsc2455 : BIT; -- auxsc2455 SIGNAL auxsc2456 : BIT; -- auxsc2456 SIGNAL auxsc2467 : BIT; -- auxsc2467 SIGNAL auxsc2468 : BIT; -- auxsc2468 SIGNAL auxsc2469 : BIT; -- auxsc2469 SIGNAL auxsc2470 : BIT; -- auxsc2470 SIGNAL auxsc2465 : BIT; -- auxsc2465 SIGNAL auxsc2472 : BIT; -- auxsc2472 SIGNAL auxsc2500 : BIT; -- auxsc2500 SIGNAL auxsc2526 : BIT; -- auxsc2526 SIGNAL auxsc2527 : BIT; -- auxsc2527 SIGNAL auxsc2524 : BIT; -- auxsc2524 SIGNAL auxsc2511 : BIT; -- auxsc2511 SIGNAL auxsc2520 : BIT; -- auxsc2520 SIGNAL auxsc2528 : BIT; -- auxsc2528 SIGNAL auxsc2529 : BIT; -- auxsc2529 SIGNAL auxsc2530 : BIT; -- auxsc2530 SIGNAL auxsc2531 : BIT; -- auxsc2531 SIGNAL auxsc2512 : BIT; -- auxsc2512 SIGNAL auxsc2532 : BIT; -- auxsc2532 SIGNAL auxsc1711 : BIT; -- auxsc1711 SIGNAL auxsc2514 : BIT; -- auxsc2514 SIGNAL auxsc2517 : BIT; -- auxsc2517 SIGNAL auxsc2508 : BIT; -- auxsc2508 SIGNAL a uxsc2516 : BIT; -- auxsc2516 SIGNAL auxsc2492 : BIT; -- auxsc2492 SIGNAL auxsc2515 : BIT; -- auxsc2515 SIGNAL auxsc2533 : BIT; -- auxsc2533 SIGNAL auxsc2534 : BIT; -- auxsc2534 SIGNAL auxsc337 : BIT; -- auxsc337 SIGNAL auxsc2556 : BIT; -- auxsc2556 SIGNAL auxsc2550 : BIT; -- auxsc2550 SIGNAL auxsc2545 : BIT; -- auxsc2545 SIGNAL auxsc2557 : BIT; -- auxsc2557 SIGNAL auxsc2549 : BIT; -- auxsc2549 SIGNAL auxsc2580 : BIT; -- auxsc2580 SIGNAL auxsc2590 : BIT; -- auxsc2590 SIGNAL auxsc2600 : BIT; -- auxsc2600 SIGNAL auxsc745 : BIT; -- auxsc745 SIGNAL auxsc2595 : BIT; -- auxsc2595 SIGNAL auxsc2596 : BIT; -- auxsc2596 SIGNAL auxsc2601 : BIT; -- auxsc2601 SIGNAL auxsc2602 : BIT; -- auxsc2602 SIGNAL auxsc2578 : BIT; -- auxsc2578 SIG NAL auxsc2594 : BIT; -- auxsc2594 SIGNAL auxsc2563 : BIT; -- auxsc2563 SIGNAL auxsc2599 : BIT; -- auxsc2599 SIGNAL auxsc2561 : BIT; -- auxsc2561 SIGNAL auxsc2606 : BIT; -- auxsc2606 SIGNAL auxsc2629 : BIT; -- auxsc2629 SIGNAL auxsc2620 : BIT; -- auxsc2620 SIGNAL auxsc2621 : BIT; -- auxsc2621 SIGNAL auxsc2622 : BIT; -- auxsc2622 SIGNAL auxsc2623 : BIT; -- auxsc2623 SIGNAL auxsc2630 : BIT; -- auxsc2630 SIGNAL auxsc2618 : BIT; -- auxsc2618 SIGNAL auxsc2631 : BIT; -- auxsc2631 SIGNAL auxsc2633 : BIT; -- auxsc2633 SIGNAL auxsc2635 : BIT; -- auxsc2635 SIGNAL auxsc2636 : BIT; -- auxsc2636 SIGNAL auxsc2641 : BIT; -- auxsc2641 SIGNAL auxsc1285 : BIT; -- auxsc1285 SIGNAL auxsc2642 : BIT; -- auxsc2642 SIGNAL auxsc2647 : BIT; -- auxsc2647%0 D SIGNAL auxsc2648 : BIT; -- auxsc2648 SIGNAL auxsc2649 : BIT; -- auxsc2649 SIGNAL auxsc2683 : BIT; -- auxsc2683 SIGNAL auxsc2676 : BIT; -- auxsc2676 SIGNAL auxsc2657 : BIT; -- auxsc2657 SIGNAL auxsc2678 : BIT; -- auxsc2678 SIGNAL auxsc2679 : BIT; -- auxsc2679 SIGNAL auxsc2680 : BIT; -- auxsc2680 SIGNAL auxsc2681 : BIT; -- auxsc2681 SIGNAL auxsc2675 : BIT; -- auxsc2675 SIGNAL auxsc2672 : BIT; -- auxsc2672 SIGNAL auxsc2682 : BIT; -- auxsc2682 SIGNAL auxsc2684 : BIT; -- auxsc2684 SIGNAL auxsc2709 : BIT; -- auxsc2709 SIGNAL auxsc2697 : BIT; -- auxsc2697 SIGNAL auxsc2725 : BIT; -- auxsc2725 SIGNAL auxsc2726 : BIT; -- auxsc2726 SIGNAL auxsc2721 : BIT; -- auxsc2721 SIGNAL auxsc2727 : BIT; -- auxsc2727 SIGNAL auxsc2728 : BIT; -- au xsc2728 SIGNAL auxsc2729 : BIT; -- auxsc2729 SIGNAL auxsc2730 : BIT; -- auxsc2730 SIGNAL auxsc2731 : BIT; -- auxsc2731 SIGNAL auxsc2710 : BIT; -- auxsc2710 SIGNAL auxsc2711 : BIT; -- auxsc2711 SIGNAL auxsc2712 : BIT; -- auxsc2712 SIGNAL auxsc2719 : BIT; -- auxsc2719 SIGNAL auxsc2713 : BIT; -- auxsc2713 SIGNAL auxsc2714 : BIT; -- auxsc2714 SIGNAL auxsc2715 : BIT; -- auxsc2715 SIGNAL auxsc2716 : BIT; -- auxsc2716 SIGNAL auxsc2732 : BIT; -- auxsc2732 SIGNAL auxsc2733 : BIT; -- auxsc2733 SIGNAL auxsc2734 : BIT; -- auxsc2734 SIGNAL auxsc2765 : BIT; -- auxsc2765 SIGNAL auxsc2763 : BIT; -- auxsc2763 SIGNAL auxsc2756 : BIT; -- auxsc2756 SIGNAL auxsc2766 : BIT; -- auxsc2766 SIGNAL auxsc2757 : BIT; -- auxsc2757 SIGNAL auxsc2767 : BIT%3 B -- auxsc2767 SIGNAL auxsc2768 : BIT; -- auxsc2768 SIGNAL auxsc2769 : BIT; -- auxsc2769 SIGNAL auxsc2770 : BIT; -- auxsc2770 SIGNAL auxsc2755 : BIT; -- auxsc2755 SIGNAL auxsc2771 : BIT; -- auxsc2771 SIGNAL auxsc2772 : BIT; -- auxsc2772 SIGNAL auxsc2773 : BIT; -- auxsc2773 SIGNAL auxsc2784 : BIT; -- auxsc2784 SIGNAL auxsc2785 : BIT; -- auxsc2785 SIGNAL auxsc2786 : BIT; -- auxsc2786 SIGNAL auxsc2790 : BIT; -- auxsc2790 SIGNAL auxsc2830 : BIT; -- auxsc2830 SIGNAL auxsc2831 : BIT; -- auxsc2831 SIGNAL auxsc2837 : BIT; -- auxsc2837 SIGNAL auxsc2829 : BIT; -- auxsc2829 SIGNAL auxsc2835 : BIT; -- auxsc2835 SIGNAL auxsc2838 : BIT; -- auxsc2838 SIGNAL auxsc2843 : BIT; -- auxsc2843 SIGNAL auxsc2826 : BIT; -- auxsc2826 SIGNAL auxsc2839 : BIT; -- auxsc2839 SIGNAL auxsc2840 : BIT; -- auxsc2840 SIGNAL auxsc2841 : BIT; -- auxsc2841 SIGNAL auxsc2834 : BIT; -- auxsc2834 SIGNAL auxsc2795 : BIT; -- auxsc2795 SIGNAL auxsc2842 : BIT; -- auxsc2842 SIGNAL auxsc2847 : BIT; -- auxsc2847 SIGNAL auxsc2853 : BIT; -- auxsc2853 SIGNAL auxsc2854 : BIT; -- auxsc2854 SIGNAL auxsc2848 : BIT; -- auxsc2848 SIGNAL auxsc2855 : BIT; -- auxsc2855 SIGNAL auxsc456 : BIT; -- auxsc456 SIGNAL auxsc444 : BIT; -- auxsc444 SIGNAL auxsc451 : BIT; -- auxsc451 SIGNAL auxsc424 : BIT; -- auxsc424 SIGNAL auxsc426 : BIT; -- auxsc426 SIGNAL auxsc123 : BIT; -- auxsc123 SIGNAL auxsc452 : BIT; -- auxsc452 SIGNAL auxsc457 : BIT; -- auxsc457 SIGNAL auxsc458 : BIT; -- auxsc458 SIGNAL auxsc462 : BIT; -- auxsc462 SIGNAL auxsc413 : BIT; -- auxsc413 SIGNAL auxsc154 : BIT; -- auxsc154 SIGNAL auxsc414 : BIT; -- auxsc414 SIGNAL auxsc433 : BIT; -- auxsc433 SIGNAL auxsc441 : BIT; -- auxsc441 SIGNAL auxsc409 : BIT; -- auxsc409 SIGNAL auxsc88 : BIT; -- auxsc88 SIGNAL auxsc89 : BIT; -- auxsc89 SIGNAL auxsc294 : BIT; -- auxsc294 SIGNAL auxsc52 : BIT; -- auxsc52 SIGNAL auxsc296 : BIT; -- auxsc296 SIGNAL auxsc80 : BIT; -- auxsc80 SIGNAL auxsc81 : BIT; -- auxsc81 SIGNAL auxsc76 : BIT; -- auxsc76 SIGNAL auxsc82 : BIT; -- auxsc82 SIGNAL auxsc83 : BIT; -- auxsc83 SIGNAL auxsc84 : BIT; -- auxsc84 SIGNAL auxsc44 : BIT; -- auxsc44 SIGNAL auxsc72 : BIT; -- auxsc72 SIGNAL auxsc73 : BIT; -- auxsc73 SIGNAL auxsc85 : BIT; -- au xsc85 SIGNAL auxsc75 : BIT; -- auxsc75 SIGNAL auxsc86 : BIT; -- auxsc86 SIGNAL auxsc87 : BIT; -- auxsc87 SIGNAL auxsc297 : BIT; -- auxsc297 SIGNAL auxsc317 : BIT; -- auxsc317 SIGNAL auxsc160 : BIT; -- auxsc160 SIGNAL auxsc381 : BIT; -- auxsc381 SIGNAL auxsc382 : BIT; -- auxsc382 SIGNAL auxsc383 : BIT; -- auxsc383 SIGNAL auxsc410 : BIT; -- auxsc410 SIGNAL auxsc385 : BIT; -- auxsc385 SIGNAL auxsc411 : BIT; -- auxsc411 SIGNAL auxsc412 : BIT; -- auxsc412 SIGNAL auxsc167 : BIT; -- auxsc167 SIGNAL auxsc389 : BIT; -- auxsc389 SIGNAL auxsc415 : BIT; -- auxsc415 SIGNAL auxsc416 : BIT; -- auxsc416 SIGNAL auxsc22 : BIT; -- auxsc22 SIGNAL auxsc372 : BIT; -- auxsc372 SIGNAL auxsc36 : BIT; -- auxsc36 SIGNAL auxsc391 : BIT;%0 9-- auxsc391 SIGNAL auxsc393 : BIT; -- auxsc393 SIGNAL auxsc417 : BIT; -- auxsc417 SIGNAL auxsc395 : BIT; -- auxsc395 SIGNAL auxsc396 : BIT; -- auxsc396 SIGNAL auxsc418 : BIT; -- auxsc418 SIGNAL auxsc436 : BIT; -- auxsc436 SIGNAL auxsc139 : BIT; -- auxsc139 SIGNAL auxsc420 : BIT; -- auxsc420 SIGNAL auxsc368 : BIT; -- auxsc368 SIGNAL auxsc369 : BIT; -- auxsc369 SIGNAL auxsc370 : BIT; -- auxsc370 SIGNAL auxsc421 : BIT; -- auxsc421 SIGNAL auxsc437 : BIT; -- auxsc437 SIGNAL auxsc442 : BIT; -- auxsc442 SIGNAL auxsc446 : BIT; -- auxsc446 SIGNAL auxsc459 : BIT; -- auxsc459 SIGNAL auxsc403 : BIT; -- auxsc403 SIGNAL auxsc366 : BIT; -- auxsc366 SIGNAL auxsc365 : BIT; -- auxsc365 SIGNAL auxsc404 : BIT; -- auxsc404 SIGNAL auxs c427 : BIT; -- auxsc427 SIGNAL auxsc359 : BIT; -- auxsc359 SIGNAL auxsc406 : BIT; -- auxsc406 SIGNAL auxsc361 : BIT; -- auxsc361 SIGNAL auxsc237 : BIT; -- auxsc237 SIGNAL auxsc339 : BIT; -- auxsc339 SIGNAL auxsc311 : BIT; -- auxsc311 SIGNAL auxsc323 : BIT; -- auxsc323 SIGNAL auxsc324 : BIT; -- auxsc324 SIGNAL auxsc340 : BIT; -- auxsc340 SIGNAL auxsc362 : BIT; -- auxsc362 SIGNAL auxsc407 : BIT; -- auxsc407 SIGNAL auxsc428 : BIT; -- auxsc428 SIGNAL auxsc448 : BIT; -- auxsc448 SIGNAL auxsc350 : BIT; -- auxsc350 SIGNAL auxsc351 : BIT; -- auxsc351 SIGNAL auxsc234 : BIT; -- auxsc234 SIGNAL auxsc209 : BIT; -- auxsc209 SIGNAL auxsc304 : BIT; -- auxsc304 SIGNAL auxsc335 : BIT; -- auxsc335 SIGNAL auxsc303 : BIT; -- auxsc303%0 D SIGNAL auxsc308 : BIT; -- auxsc308 SIGNAL auxsc309 : BIT; -- auxsc309 SIGNAL auxsc109 : BIT; -- auxsc109 SIGNAL auxsc328 : BIT; -- auxsc328 SIGNAL auxsc336 : BIT; -- auxsc336 SIGNAL auxsc228 : BIT; -- auxsc228 SIGNAL auxsc398 : BIT; -- auxsc398 SIGNAL auxsc430 : BIT; -- auxsc430 SIGNAL auxsc354 : BIT; -- auxsc354 SIGNAL auxsc355 : BIT; -- auxsc355 SIGNAL auxsc400 : BIT; -- auxsc400 SIGNAL auxsc283 : BIT; -- auxsc283 SIGNAL auxsc284 : BIT; -- auxsc284 SIGNAL auxsc285 : BIT; -- auxsc285 SIGNAL auxsc301 : BIT; -- auxsc301 SIGNAL auxsc319 : BIT; -- auxsc319 SIGNAL auxsc326 : BIT; -- auxsc326 SIGNAL auxsc330 : BIT; -- auxsc330 SIGNAL auxsc331 : BIT; -- auxsc331 SIGNAL auxsc290 : BIT; -- auxsc290 SIGNAL auxsc282 : BIT%3 B -- auxsc282 SIGNAL auxsc279 : BIT; -- auxsc279 SIGNAL auxsc280 : BIT; -- auxsc280 SIGNAL auxsc281 : BIT; -- auxsc281 SIGNAL auxsc255 : BIT; -- auxsc255 SIGNAL auxsc251 : BIT; -- auxsc251 SIGNAL auxsc291 : BIT; -- auxsc291 SIGNAL auxsc292 : BIT; -- auxsc292 SIGNAL auxsc306 : BIT; -- auxsc306 SIGNAL auxsc315 : BIT; -- auxsc315 SIGNAL auxsc332 : BIT; -- auxsc332 SIGNAL auxsc333 : BIT; -- auxsc333 SIGNAL auxsc334 : BIT; -- auxsc334 SIGNAL auxsc344 : BIT; -- auxsc344 SIGNAL auxsc357 : BIT; -- auxsc357 SIGNAL auxsc401 : BIT; -- auxsc401 SIGNAL auxsc431 : BIT; -- auxsc431 SIGNAL auxsc449 : BIT; -- auxsc449 SIGNAL auxsc460 : BIT; -- auxsc460 SIGNAL auxsc463 : BIT; -- auxsc463 SIGNAL auxsc276 : BIT; -- auxsc276 SIGNAL a uxsc798 : BIT; -- auxsc798 SIGNAL auxsc792 : BIT; -- auxsc792 SIGNAL auxsc799 : BIT; -- auxsc799 SIGNAL auxsc746 : BIT; -- auxsc746 SIGNAL auxsc711 : BIT; -- auxsc711 SIGNAL auxsc712 : BIT; -- auxsc712 SIGNAL auxsc734 : BIT; -- auxsc734 SIGNAL auxsc735 : BIT; -- auxsc735 SIGNAL auxsc747 : BIT; -- auxsc747 SIGNAL auxsc748 : BIT; -- auxsc748 SIGNAL auxsc765 : BIT; -- auxsc765 SIGNAL auxsc782 : BIT; -- auxsc782 SIGNAL auxsc732 : BIT; -- auxsc732 SIGNAL auxsc768 : BIT; -- auxsc768 SIGNAL auxsc681 : BIT; -- auxsc681 SIGNAL auxsc688 : BIT; -- auxsc688 SIGNAL auxsc689 : BIT; -- auxsc689 SIGNAL auxsc687 : BIT; -- auxsc687 SIGNAL auxsc682 : BIT; -- auxsc682 SIGNAL auxsc683 : BIT; -- auxsc683 SIGNAL auxsc684 : BIT; -- auxsc68 4 SIGNAL auxsc685 : BIT; -- auxsc685 SIGNAL auxsc686 : BIT; -- auxsc686 SIGNAL auxsc700 : BIT; -- auxsc700 SIGNAL auxsc729 : BIT; -- auxsc729 SIGNAL auxsc528 : BIT; -- auxsc528 SIGNAL auxsc529 : BIT; -- auxsc529 SIGNAL auxsc530 : BIT; -- auxsc530 SIGNAL auxsc531 : BIT; -- auxsc531 SIGNAL auxsc517 : BIT; -- auxsc517 SIGNAL auxsc532 : BIT; -- auxsc532 SIGNAL auxsc533 : BIT; -- auxsc533 SIGNAL auxsc501 : BIT; -- auxsc501 SIGNAL auxsc520 : BIT; -- auxsc520 SIGNAL auxsc534 : BIT; -- auxsc534 SIGNAL auxsc522 : BIT; -- auxsc522 SIGNAL auxsc510 : BIT; -- auxsc510 SIGNAL auxsc523 : BIT; -- auxsc523 SIGNAL auxsc535 : BIT; -- auxsc535 SIGNAL auxsc511 : BIT; -- auxsc511 SIGNAL auxsc512 : BIT; -- auxsc512 SIGNAL auxsc503 : BI T; -- auxsc503 SIGNAL auxsc536 : BIT; -- auxsc536 SIGNAL auxsc706 : BIT; -- auxsc706 SIGNAL auxsc730 : BIT; -- auxsc730 SIGNAL auxsc731 : BIT; -- auxsc731 SIGNAL auxsc590 : BIT; -- auxsc590 SIGNAL auxsc701 : BIT; -- auxsc701 SIGNAL auxsc702 : BIT; -- auxsc702 SIGNAL auxsc725 : BIT; -- auxsc725 SIGNAL auxsc726 : BIT; -- auxsc726 SIGNAL auxsc727 : BIT; -- auxsc727 SIGNAL auxsc767 : BIT; -- auxsc767 SIGNAL auxsc781 : BIT; -- auxsc781 SIGNAL auxsc786 : BIT; -- auxsc786 SIGNAL auxsc740 : BIT; -- auxsc740 SIGNAL auxsc557 : BIT; -- auxsc557 SIGNAL auxsc755 : BIT; -- auxsc755 SIGNAL auxsc585 : BIT; -- auxsc585 SIGNAL auxsc753 : BIT; -- auxsc753 SIGNAL auxsc564 : BIT; -- auxsc564 SIGNAL auxsc750 : BIT; -- auxsc750 SIGNA L auxsc751 : BIT; -- auxsc751 SIGNAL auxsc752 : BIT; -- auxsc752 SIGNAL auxsc773 : BIT; -- auxsc773 SIGNAL auxsc784 : BIT; -- auxsc784 SIGNAL auxsc787 : BIT; -- auxsc787 SIGNAL auxsc794 : BIT; -- auxsc794 SIGNAL auxsc621 : BIT; -- auxsc621 SIGNAL auxsc716 : BIT; -- auxsc716 SIGNAL auxsc717 : BIT; -- auxsc717 SIGNAL auxsc741 : BIT; -- auxsc741 SIGNAL auxsc761 : BIT; -- auxsc761 SIGNAL auxsc622 : BIT; -- auxsc622 SIGNAL auxsc775 : BIT; -- auxsc775 SIGNAL auxsc629 : BIT; -- auxsc629 SIGNAL auxsc692 : BIT; -- auxsc692 SIGNAL auxsc697 : BIT; -- auxsc697 SIGNAL auxsc698 : BIT; -- auxsc698 SIGNAL auxsc705 : BIT; -- auxsc705 SIGNAL auxsc722 : BIT; -- auxsc722 SIGNAL auxsc723 : BIT; -- auxsc723 SIGNAL auxsc724 : BIT; -- auxs c724 SIGNAL auxsc763 : BIT; -- auxsc763 SIGNAL auxsc776 : BIT; -- auxsc776 SIGNAL auxsc789 : BIT; -- auxsc789 SIGNAL auxsc756 : BIT; -- auxsc756 SIGNAL auxsc715 : BIT; -- auxsc715 SIGNAL auxsc691 : BIT; -- auxsc691 SIGNAL auxsc693 : BIT; -- auxsc693 SIGNAL auxsc694 : BIT; -- auxsc694 SIGNAL auxsc668 : BIT; -- auxsc668 SIGNAL auxsc669 : BIT; -- auxsc669 SIGNAL auxsc670 : BIT; -- auxsc670 SIGNAL auxsc677 : BIT; -- auxsc677 SIGNAL auxsc695 : BIT; -- auxsc695 SIGNAL auxsc696 : BIT; -- auxsc696 SIGNAL auxsc704 : BIT; -- auxsc704 SIGNAL auxsc757 : BIT; -- auxsc757 SIGNAL auxsc778 : BIT; -- auxsc778 SIGNAL auxsc721 : BIT; -- auxsc721 SIGNAL auxsc759 : BIT; -- auxsc759 SIGNAL auxsc779 : BIT; -- auxsc779 SIGNAL auxsc790 : BIT; -- auxsc790 SIGNAL auxsc795 : BIT; -- auxsc795 SIGNAL auxsc800 : BIT; -- auxsc800 SIGNAL auxsc801 : BIT; -- auxsc801 SIGNAL auxsc666 : BIT; -- auxsc666 SIGNAL auxsc1049 : BIT; -- auxsc1049 SIGNAL auxsc1050 : BIT; -- auxsc1050 SIGNAL auxsc1051 : BIT; -- auxsc1051 SIGNAL auxsc1052 : BIT; -- auxsc1052 SIGNAL auxsc1053 : BIT; -- auxsc1053 SIGNAL auxsc1008 : BIT; -- auxsc1008 SIGNAL auxsc985 : BIT; -- auxsc985 SIGNAL auxsc986 : BIT; -- auxsc986 SIGNAL auxsc987 : BIT; -- auxsc987 SIGNAL auxsc959 : BIT; -- auxsc959 SIGNAL auxsc1007 : BIT; -- auxsc1007 SIGNAL auxsc1036 : BIT; -- auxsc1036 SIGNAL auxsc1004 : BIT; -- auxsc1004 SIGNAL auxsc1005 : BIT; -- auxsc1005 SIGNAL auxsc1035 : BIT; -- auxsc1035 SIGNAL auxsc1037 : BIT;% 09-- auxsc1037 SIGNAL auxsc1057 : BIT; -- auxsc1057 SIGNAL auxsc1031 : BIT; -- auxsc1031 SIGNAL auxsc1023 : BIT; -- auxsc1023 SIGNAL auxsc1032 : BIT; -- auxsc1032 SIGNAL auxsc548 : BIT; -- auxsc548 SIGNAL auxsc998 : BIT; -- auxsc998 SIGNAL auxsc1033 : BIT; -- auxsc1033 SIGNAL auxsc1034 : BIT; -- auxsc1034 SIGNAL auxsc1058 : BIT; -- auxsc1058 SIGNAL auxsc1059 : BIT; -- auxsc1059 SIGNAL auxsc1027 : BIT; -- auxsc1027 SIGNAL auxsc895 : BIT; -- auxsc895 SIGNAL auxsc978 : BIT; -- auxsc978 SIGNAL auxsc989 : BIT; -- auxsc989 SIGNAL auxsc1019 : BIT; -- auxsc1019 SIGNAL auxsc1026 : BIT; -- auxsc1026 SIGNAL auxsc1039 : BIT; -- auxsc1039 SIGNAL auxsc1040 : BIT; -- auxsc1040 SIGNAL auxsc1054 : BIT; -- auxsc1054 SIGNAL auxsc909 : BIT; -- auxsc909 SIGNAL auxsc1016 : BIT; -- auxsc1016 SIGNAL auxsc1017 : BIT; -- auxsc1017 SIGNAL auxsc1043 : BIT; -- auxsc1043 SIGNAL auxsc1013 : BIT; -- auxsc1013 SIGNAL auxsc1012 : BIT; -- auxsc1012 SIGNAL auxsc981 : BIT; -- auxsc981 SIGNAL auxsc982 : BIT; -- auxsc982 SIGNAL auxsc973 : BIT; -- auxsc973 SIGNAL auxsc972 : BIT; -- auxsc972 SIGNAL auxsc974 : BIT; -- auxsc974 SIGNAL auxsc983 : BIT; -- auxsc983 SIGNAL auxsc984 : BIT; -- auxsc984 SIGNAL auxsc988 : BIT; -- auxsc988 SIGNAL auxsc933 : BIT; -- auxsc933 SIGNAL auxsc1011 : BIT; -- auxsc1011 SIGNAL auxsc1002 : BIT; -- auxsc1002 SIGNAL auxsc1014 : BIT; -- auxsc1014 SIGNAL auxsc1042 : BIT; -- auxsc1042 SIGNAL auxsc1055 : BIT; -- auxsc1055 SIGNAL auxsc1056 : BIT; -- auxsc10 56 SIGNAL auxsc1063 : BIT; -- auxsc1063 SIGNAL auxsc1064 : BIT; -- auxsc1064 SIGNAL auxsc1066 : BIT; -- auxsc1066 SIGNAL auxsc970 : BIT; -- auxsc970 SIGNAL auxsc1292 : BIT; -- auxsc1292 SIGNAL auxsc1282 : BIT; -- auxsc1282 SIGNAL auxsc1278 : BIT; -- auxsc1278 SIGNAL auxsc1273 : BIT; -- auxsc1273 SIGNAL auxsc1279 : BIT; -- auxsc1279 SIGNAL auxsc1131 : BIT; -- auxsc1131 SIGNAL auxsc1271 : BIT; -- auxsc1271 SIGNAL auxsc1280 : BIT; -- auxsc1280 SIGNAL auxsc1283 : BIT; -- auxsc1283 SIGNAL auxsc1284 : BIT; -- auxsc1284 SIGNAL auxsc1253 : BIT; -- auxsc1253 SIGNAL auxsc1254 : BIT; -- auxsc1254 SIGNAL auxsc1276 : BIT; -- auxsc1276 SIGNAL auxsc1217 : BIT; -- auxsc1217 SIGNAL auxsc1233 : BIT; -- auxsc1233 SIGNAL auxsc1234 : BIT; -- auxsc1234 SIGNAL auxsc1160 : BIT; -- auxsc1160 SIGNAL auxsc1256 : BIT; -- auxsc1256 SIGNAL auxsc1257 : BIT; -- auxsc1257 SIGNAL auxsc1286 : BIT; -- auxsc1286 SIGNAL auxsc1287 : BIT; -- auxsc1287 SIGNAL auxsc1293 : BIT; -- auxsc1293 SIGNAL auxsc1244 : BIT; -- auxsc1244 SIGNAL auxsc1262 : BIT; -- auxsc1262 SIGNAL auxsc1243 : BIT; -- auxsc1243 SIGNAL auxsc1122 : BIT; -- auxsc1122 SIGNAL auxsc1123 : BIT; -- auxsc1123 SIGNAL auxsc1087 : BIT; -- auxsc1087 SIGNAL auxsc1127 : BIT; -- auxsc1127 SIGNAL auxsc1109 : BIT; -- auxsc1109 SIGNAL auxsc1110 : BIT; -- auxsc1110 SIGNAL auxsc1117 : BIT; -- auxsc1117 SIGNAL auxsc1118 : BIT; -- auxsc1118 SIGNAL auxsc1105 : BIT; -- auxsc1105 SIGNAL auxsc1113 : BIT; -- auxsc1113 SIGNAL auxsc1107 : BIT ; -- auxsc1107 SIGNAL auxsc1114 : BIT; -- auxsc1114 SIGNAL auxsc1115 : BIT; -- auxsc1115 SIGNAL auxsc1120 : BIT; -- auxsc1120 SIGNAL auxsc1102 : BIT; -- auxsc1102 SIGNAL auxsc1235 : BIT; -- auxsc1235 SIGNAL auxsc1236 : BIT; -- auxsc1236 SIGNAL auxsc1237 : BIT; -- auxsc1237 SIGNAL auxsc1263 : BIT; -- auxsc1263 SIGNAL auxsc1264 : BIT; -- auxsc1264 SIGNAL auxsc1265 : BIT; -- auxsc1265 SIGNAL auxsc1214 : BIT; -- auxsc1214 SIGNAL auxsc1215 : BIT; -- auxsc1215 SIGNAL auxsc1210 : BIT; -- auxsc1210 SIGNAL auxsc1211 : BIT; -- auxsc1211 SIGNAL auxsc1212 : BIT; -- auxsc1212 SIGNAL auxsc1213 : BIT; -- auxsc1213 SIGNAL auxsc1216 : BIT; -- auxsc1216 SIGNAL auxsc1222 : BIT; -- auxsc1222 SIGNAL auxsc1223 : BIT; -- auxsc1223 SIGNAL auxsc122 5 : BIT; -- auxsc1225 SIGNAL auxsc1128 : BIT; -- auxsc1128 SIGNAL auxsc1221 : BIT; -- auxsc1221 SIGNAL auxsc1227 : BIT; -- auxsc1227 SIGNAL auxsc1240 : BIT; -- auxsc1240 SIGNAL auxsc1228 : BIT; -- auxsc1228 SIGNAL auxsc1229 : BIT; -- auxsc1229 SIGNAL auxsc1230 : BIT; -- auxsc1230 SIGNAL auxsc1241 : BIT; -- auxsc1241 SIGNAL auxsc1242 : BIT; -- auxsc1242 SIGNAL auxsc1250 : BIT; -- auxsc1250 SIGNAL auxsc1251 : BIT; -- auxsc1251 SIGNAL auxsc1266 : BIT; -- auxsc1266 SIGNAL auxsc1289 : BIT; -- auxsc1289 SIGNAL auxsc1294 : BIT; -- auxsc1294 SIGNAL auxsc1295 : BIT; -- auxsc1295 SIGNAL auxsc1207 : BIT; -- auxsc1207 SIGNAL auxsc1459 : BIT; -- auxsc1459 SIGNAL auxsc1445 : BIT; -- auxsc1445 SIGNAL auxsc1446 : BIT; -- auxsc1446 SIGNAL auxsc1395 : BIT; -- auxsc1395 SIGNAL auxsc1485 : BIT; -- auxsc1485 SIGNAL auxsc1456 : BIT; -- auxsc1456 SIGNAL auxsc1457 : BIT; -- auxsc1457 SIGNAL auxsc1466 : BIT; -- auxsc1466 SIGNAL auxsc1467 : BIT; -- auxsc1467 SIGNAL auxsc1486 : BIT; -- auxsc1486 SIGNAL auxsc1469 : BIT; -- auxsc1469 SIGNAL auxsc1470 : BIT; -- auxsc1470 SIGNAL auxsc1453 : BIT; -- auxsc1453 SIGNAL auxsc1443 : BIT; -- auxsc1443 SIGNAL auxsc1444 : BIT; -- auxsc1444 SIGNAL auxsc1439 : BIT; -- auxsc1439 SIGNAL auxsc1440 : BIT; -- auxsc1440 SIGNAL auxsc1416 : BIT; -- auxsc1416 SIGNAL auxsc1441 : BIT; -- auxsc1441 SIGNAL auxsc1442 : BIT; -- auxsc1442 SIGNAL auxsc1454 : BIT; -- auxsc1454 SIGNAL auxsc1471 : BIT; -- auxsc1471 SIGNAL auxsc1487 : BIT; -- auxsc1487 %0 A SIGNAL auxsc1488 : BIT; -- auxsc1488 SIGNAL auxsc1489 : BIT; -- auxsc1489 SIGNAL auxsc1429 : BIT; -- auxsc1429 SIGNAL auxsc1507 : BIT; -- auxsc1507 SIGNAL auxsc1476 : BIT; -- auxsc1476 SIGNAL auxsc1460 : BIT; -- auxsc1460 SIGNAL auxsc1461 : BIT; -- auxsc1461 SIGNAL auxsc1462 : BIT; -- auxsc1462 SIGNAL auxsc1477 : BIT; -- auxsc1477 SIGNAL auxsc1516 : BIT; -- auxsc1516 SIGNAL auxsc1517 : BIT; -- auxsc1517 SIGNAL auxsc1373 : BIT; -- auxsc1373 SIGNAL auxsc1518 : BIT; -- auxsc1518 SIGNAL auxsc1519 : BIT; -- auxsc1519 SIGNAL auxsc1520 : BIT; -- auxsc1520 SIGNAL auxsc1521 : BIT; -- auxsc1521 SIGNAL auxsc1522 : BIT; -- auxsc1522 SIGNAL auxsc1523 : BIT; -- auxsc1523 SIGNAL auxsc1524 : BIT; -- auxsc1524 SIGNAL auxsc1529 : BIT; -- auxsc 1529 SIGNAL auxsc1448 : BIT; -- auxsc1448 SIGNAL auxsc1498 : BIT; -- auxsc1498 SIGNAL auxsc1480 : BIT; -- auxsc1480 SIGNAL auxsc1481 : BIT; -- auxsc1481 SIGNAL auxsc1482 : BIT; -- auxsc1482 SIGNAL auxsc1497 : BIT; -- auxsc1497 SIGNAL auxsc1525 : BIT; -- auxsc1525 SIGNAL auxsc1493 : BIT; -- auxsc1493 SIGNAL auxsc1494 : BIT; -- auxsc1494 SIGNAL auxsc1464 : BIT; -- auxsc1464 SIGNAL auxsc1465 : BIT; -- auxsc1465 SIGNAL auxsc1495 : BIT; -- auxsc1495 SIGNAL auxsc1496 : BIT; -- auxsc1496 SIGNAL auxsc1526 : BIT; -- auxsc1526 SIGNAL auxsc1530 : BIT; -- auxsc1530 SIGNAL auxsc1500 : BIT; -- auxsc1500 SIGNAL auxsc1501 : BIT; -- auxsc1501 SIGNAL auxsc1502 : BIT; -- auxsc1502 SIGNAL auxsc1503 : BIT; -- auxsc1503 SIGNAL auxsc1531 : BIT;%0 9-- auxsc1531 SIGNAL auxsc1532 : BIT; -- auxsc1532 SIGNAL auxsc1433 : BIT; -- auxsc1433 SIGNAL auxsc1536 : BIT; -- auxsc1536 SIGNAL auxsc1538 : BIT; -- auxsc1538 SIGNAL auxsc1437 : BIT; -- auxsc1437 SIGNAL auxsc1746 : BIT; -- auxsc1746 SIGNAL auxsc1743 : BIT; -- auxsc1743 SIGNAL auxsc1747 : BIT; -- auxsc1747 SIGNAL auxsc1735 : BIT; -- auxsc1735 SIGNAL auxsc1736 : BIT; -- auxsc1736 SIGNAL auxsc1737 : BIT; -- auxsc1737 SIGNAL auxsc1738 : BIT; -- auxsc1738 SIGNAL auxsc1739 : BIT; -- auxsc1739 SIGNAL auxsc1740 : BIT; -- auxsc1740 SIGNAL auxsc1741 : BIT; -- auxsc1741 SIGNAL auxsc1706 : BIT; -- auxsc1706 SIGNAL auxsc1707 : BIT; -- auxsc1707 SIGNAL auxsc1719 : BIT; -- auxsc1719 SIGNAL auxsc1720 : BIT; -- auxsc1720 SIGNAL auxsc1700 : BIT; -- auxsc1700 SIGNAL auxsc1698 : BIT; -- auxsc1698 SIGNAL auxsc1699 : BIT; -- auxsc1699 SIGNAL auxsc1721 : BIT; -- auxsc1721 SIGNAL auxsc1727 : BIT; -- auxsc1727 SIGNAL auxsc1712 : BIT; -- auxsc1712 SIGNAL auxsc1713 : BIT; -- auxsc1713 SIGNAL auxsc1724 : BIT; -- auxsc1724 SIGNAL auxsc1705 : BIT; -- auxsc1705 SIGNAL auxsc1716 : BIT; -- auxsc1716 SIGNAL auxsc1717 : BIT; -- auxsc1717 SIGNAL auxsc1725 : BIT; -- auxsc1725 SIGNAL auxsc1728 : BIT; -- auxsc1728 SIGNAL auxsc1742 : BIT; -- auxsc1742 SIGNAL auxsc1744 : BIT; -- auxsc1744 SIGNAL auxsc1748 : BIT; -- auxsc1748 SIGNAL auxsc1696 : BIT; -- auxsc1696 SIGNAL auxreg7 : BIT; -- auxreg7 SIGNAL auxreg6 : BIT; -- auxreg6 SIGNAL auxreg5 : BIT; -- auxreg5 SIGNAL auxreg4 : BIT% 3B -- auxreg4 SIGNAL auxreg3 : BIT; -- auxreg3 SIGNAL auxreg2 : BIT; -- auxreg2 BEGIN excp_0 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => excp(0), i2 => auxsc1773, i1 => auxsc171, i0 => auxsc1772); excp_1 : nao2o22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => excp(1), i3 => auxreg7, i2 => auxsc1784, i1 => auxsc1785, i0 => auxsc1046); excp_2 : oa2a2a23_x2 PORT MAP ( vss => vss, vdd => vdd, q => excp(2), i5 => auxsc1806, i4 => auxsc1804, i3 => auxsc1809, i2 => auxsc1808, i1 => auxreg7, i0 => auxreg6); excp_3 : nao2o22_x1% 0D PORT MAP ( vss => vss, vdd => vdd, nq => excp(3), i3 => auxreg7, i2 => auxsc1831, i1 => auxsc1832, i0 => auxsc1046); excp_4 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => excp(4), i1 => auxsc1858, i0 => auxsc1773); excp_5 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => excp(5), i2 => auxsc1900, i1 => auxsc1876, i0 => auxsc1926); excp_6 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => excp(6), i2 => auxsc1948, i1 => auxsc1940, i0 => auxsc1939); ctladr : o4_x2 PORT MAP ( vss => vss, vd d => vdd, q => ctladr, i3 => auxsc1951, i2 => auxsc1952, i1 => auxsc1956, i0 => auxsc1942); ctlrw_0 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => ctlrw(0), i2 => auxsc1962, i1 => auxreg6, i0 => auxsc1961); ctlrw_1 : a3_x2 PORT MAP ( vss => vss, vdd => vdd, q => ctlrw(1), i2 => auxsc1967, i1 => auxreg5, i0 => auxsc754); ctlrw_2 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => ctlrw(2), i1 => auxsc1970, i0 => auxsc1969); ctlrw_3 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => ctlrw(3), i1 =% 3E aux733_a, i0 => auxsc1973); ctlrw_4 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => ctlrw(4), i1 => auxsc2011, i0 => auxsc128); wenable_0 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => wenable(0), i1 => auxsc2065, i0 => auxsc128); wenable_1 : a3_x2 PORT MAP ( vss => vss, vdd => vdd, q => wenable(1), i2 => auxsc2089, i1 => auxsc2085, i0 => auxsc128); wenable_2 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => wenable(2), i1 => auxsc2103, i0 => auxsc128); wenable_3 : nao2o22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => wenable(3), i3 => auxsc2133, i2 => frz, i1 => auxsc171, i0 => auxsc2132); wenable_4 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => wenable(4), i1 => aux733_a, i0 => auxsc2136); wenable_5 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => wenable(5), i1 => aux733_a, i0 => auxsc2142); wenable_6 : a3_x2 PORT MAP ( vss => vss, vdd => vdd, q => wenable(6), i2 => aux752_a, i1 => aux577_a, i0 => auxsc128); wenable_7 : a4_x2 PORT MAP ( vss => vss, vdd => vdd, q => wenable(7), i3 => aux752_a,% 0D i2 => aux592_a, i1 => auxreg5, i0 => auxsc128); wenable_8 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => wenable(8), i1 => auxsc2167, i0 => auxsc128); wenable_9 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => wenable(9), i3 => auxsc2207, i2 => auxsc2204, i1 => aux564_a, i0 => auxsc128); wenable_10 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => wenable(10), i2 => auxsc128, i1 => auxsc2267, i0 => auxsc2266); ctlalu_0 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => ctlalu(0), i2 => auxsc2299, i1 => auxreg7, i0 => auxsc2291); ctlalu_1 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => ctlalu(1), i1 => auxsc2349, i0 => auxsc2343); ctlalu_2 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => ctlalu(2), i2 => auxreg7, i1 => auxsc2387, i0 => auxsc2384); ctlalu_3 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => ctlalu(3), i1 => auxsc2343, i0 => auxsc2426); ctlalu_4 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => ctlalu(4), i2 => auxsc2456, i1 => auxreg7, i0 => auxsc2455); ctlalu_5 : o2_x2 PORT MAP ( % 0A vss => vss, vdd => vdd, q => ctlalu(5), i1 => auxreg7, i0 => auxsc2472); ctlopy_0 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => ctlopy(0), i1 => auxsc2534, i0 => auxsc2531); ctlopy_1 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => ctlopy(1), i2 => auxsc2549, i1 => auxreg7, i0 => auxreg6); ctlopy_2 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => ctlopy(2), i1 => auxreg7, i0 => auxsc2200); ctlopy_3 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => ctlopy(3), i2 => auxsc2606, i1 => auxreg 7, i0 => auxsc2602); ctlopy_4 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => ctlopy(4), i2 => auxsc2636, i1 => auxsc171, i0 => auxsc2618); ctlopy_5 : nao2o22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => ctlopy(5), i3 => auxsc2642, i2 => auxsc27, i1 => auxsc1285, i0 => auxsc2641); ctlopy_6 : nao2o22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => ctlopy(6), i3 => auxsc2649, i2 => auxsc2648, i1 => auxsc1940, i0 => auxsc2647); ctlopx_0 : oa2a2a23_x2 PORT MAP ( vss => vss, vdd => vdd, q => ctlopx(0), i5 => auxsc1 71, i4 => auxsc2684, i3 => aux740_a, i2 => auxsc2657, i1 => auxreg6, i0 => auxsc2683); ctlopx_1 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => ctlopx(1), i2 => auxsc2734, i1 => auxsc2728, i0 => auxsc2726); ctlopx_2 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => ctlopx(2), i1 => auxsc2773, i0 => auxsc2770); ctlopx_3 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => ctlopx(3), i1 => auxreg7, i0 => auxsc2786); ctlopx_4 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => ctlopx(4), i1 => auxsc2790, i0 => auxsc1632); ctlopx_5 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => ctlopx(5), i1 => auxsc1632, i0 => aux622_a); ctlopx_6 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => ctlopx(6), i2 => auxsc2847, i1 => auxreg7, i0 => auxsc2843); ctlopx_7 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => ctlopx(7), i2 => auxsc2848, i1 => auxreg7, i0 => auxsc2854); ctlopx_8 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => ctlopx(8), i1 => auxsc1809, i0 => auxsc2855); auxsc1696 : noa2a22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1696, i3 => auxsc1748, i2 => auxsc1747, i1 => auxsc1746, i0 => test); auxsc1748 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1748, i1 => auxsc1744, i0 => frz); auxsc1744 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1744, i3 => auxsc1742, i2 => auxsc1741, i1 => auxsc1740, i0 => auxsc171); auxsc1742 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1742, i3 => auxsc1728, i2 => auxsc423, i1 => auxsc1727, i0 => auxreg4); auxsc1728 : noa22_x1 PORT MAP ( vss => vss, %0 A vdd => vdd, nq => auxsc1728, i2 => auxsc1725, i1 => auxsc1705, i0 => auxsc1724); auxsc1725 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1725, i2 => auxreg5, i1 => auxsc1717, i0 => auxsc1716); auxsc1717 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1717, i1 => auxreg6, i0 => auxsc213); auxsc1716 : na3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1716, i2 => auxreg6, i1 => aux622_a, i0 => auxsc234); auxsc1705 : oa2a22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1705, i3 => auxsc27, i2 => aux601_a, i1 => auxreg6, i0 => auxsc1704); auxsc1724 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1724, i1 => auxsc352, i0 => auxsc1713); auxsc1713 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1713, i => auxsc1712); auxsc1712 : on12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1712, i1 => auxreg2, i0 => rqs); auxsc1727 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1727, i3 => auxsc1721, i2 => auxreg5, i1 => auxsc1720, i0 => auxsc1719); auxsc1721 : no2_x1 PORT MAP ( vss = > vss, vdd => vdd, nq => auxsc1721, i1 => auxsc1699, i0 => auxsc1700); auxsc1699 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1699, i1 => auxreg6, i0 => auxsc1698); auxsc1698 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1698, i => auxsc1628); auxsc1700 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1700, i1 => auxsc348, i0 => auxreg6); auxsc1720 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1720, i2 => auxreg6, i1 => auxsc352, i0 => auxsc1709); auxsc1719 : a2_x2 PORT MAP ( %0 A vss => vss, vdd => vdd, q => auxsc1719, i1 => auxsc1707, i0 => auxsc1706); auxsc1707 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1707, i1 => auxsc471, i0 => ir_opcod(9)); auxsc1706 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1706, i2 => ir_opcod(8), i1 => auxsc471, i0 => ir_opcod(9)); auxsc1741 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1741, i => auxsc171); auxsc1740 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1740, i => auxsc1739); auxsc1739 : on12_x1 PORT MAP (%0 D vss => vss, vdd => vdd, q => auxsc1739, i1 => auxreg6, i0 => auxsc1738); auxsc1738 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1738, i2 => auxsc1737, i1 => auxsc1732, i0 => auxsc1651); auxsc1737 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1737, i2 => auxsc423, i1 => auxsc1736, i0 => auxsc1735); auxsc1736 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1736, i1 => auxreg5, i0 => auxsc1711); auxsc1735 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1735, i1 => auxreg5, i0 => auxsc703); auxsc1747 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1747, i1 => auxsc456, i0 => auxsc1743); auxsc1743 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1743, i1 => frz, i0 => auxsc171); auxsc1746 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1746, i => scin); auxsc1437 : nao2o22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1437, i3 => auxsc1538, i2 => auxsc456, i1 => auxsc454, i0 => auxsc27); auxsc1538 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1538% 2C i2 => auxsc1536, i1 => auxsc1433, i0 => auxsc128); auxsc1536 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1536, i2 => auxsc128, i1 => auxsc792, i0 => auxsc352); auxsc1433 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1433, i2 => auxsc1532, i1 => auxsc1529, i0 => auxreg7); auxsc1532 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1532, i2 => auxsc171, i1 => auxsc1531, i0 => auxsc1530); auxsc1531 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1531, i2 => auxreg4, i1 => auxsc1503, i0 => auxsc1500); auxsc1503 : no4_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1503, i3 => auxsc1502, i2 => auxsc1501, i1 => auxsc6, i0 => auxsc1488); auxsc1502 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1502, i1 => auxreg3, i0 => auxreg6); auxsc1501 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1501, i2 => auxsc234, i1 => auxreg3, i0 => scout); auxsc1500 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1500, i2 => auxsc27, i1 => auxsc106, i0 => scout); auxsc1530 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1530, i2 => auxreg4, i1 => auxsc1526, i0 => auxsc1525); auxsc1526 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1526, i1 => auxsc1496, i0 => auxsc1494); auxsc1496 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1496, i2 => auxsc27, i1 => auxsc1495, i0 => scout); auxsc1495 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1495, i1 => auxreg3, i0 => auxsc1465); auxsc1465 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1465, i => auxsc1464); auxsc1464 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1464, i1 => auxreg2, i0 => auxsc109); auxsc1494 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1494, i1 => auxreg2, i0 => auxsc1493); auxsc1493 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1493, i1 => auxsc27, i0 => auxreg5); auxsc1525 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1525, i2 => auxsc352, i1 => auxsc1497, i0 => auxsc1498); auxsc1497 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1497 , i2 => auxsc1006, i1 => auxsc1482, i0 => auxsc1480); auxsc1482 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1482, i1 => auxreg3, i0 => auxsc1481); auxsc1481 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1481, i2 => auxreg2, i1 => scout, i0 => auxsc691); auxsc1480 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1480, i1 => auxsc14, i0 => rqs); auxsc1498 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1498, i1 => auxsc1478, i0 => auxsc1448); auxsc1448 : ao2o22_x2 PORT MAP ( v ss => vss, vdd => vdd, q => auxsc1448, i3 => auxsc1319, i2 => ir_opcod(17), i1 => auxsc1318, i0 => auxsc50); auxsc1529 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1529, i2 => auxsc1524, i1 => auxsc423, i0 => auxsc1429); auxsc1524 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1524, i1 => auxreg4, i0 => auxsc1523); auxsc1523 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1523, i2 => auxsc1522, i1 => auxsc1517, i0 => auxsc1507); auxsc1522 : oa2a22_x2 PORT MAP ( vss => vss, vdd => vdd,%0 D q => auxsc1522, i3 => auxsc1521, i2 => auxsc352, i1 => auxsc1373, i0 => auxsc1488); auxsc1521 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1521, i1 => auxsc1520, i0 => auxsc1518); auxsc1520 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1520, i2 => auxsc1519, i1 => auxsc27, i0 => rqs); auxsc1519 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1519, i1 => aux613_a, i0 => auxsc1322); auxsc1518 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1518, i1 => auxsc739, i0 => auxreg6); auxsc1373 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1373, i2 => auxsc27, i1 => auxreg3, i0 => aux567_a); auxsc1517 : a3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1517, i2 => auxsc343, i1 => auxsc1516, i0 => auxsc1488); auxsc1516 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1516, i1 => auxreg3, i0 => auxsc1477); auxsc1477 : oa2a22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1477, i3 => auxreg2, i2 => auxsc1462, i1 => auxsc10, i0 => auxsc1476); auxsc1462 : inv_x1 PORT MAP ( vss =%3 E vss, vdd => vdd, nq => auxsc1462, i => auxsc1461); auxsc1461 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1461, i1 => scout, i0 => auxsc1460); auxsc1460 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1460, i1 => auxsc109, i0 => auxsc304); auxsc1476 : a4_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1476, i3 => auxsc690, i2 => auxsc21, i1 => auxsc50, i0 => ir_opcod(16)); auxsc1507 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1507, i1 => aux568_a, i0 => auxreg6); auxsc1429 : n ao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1429, i2 => auxsc1489, i1 => auxsc1485, i0 => auxsc352); auxsc1489 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1489, i2 => auxsc1488, i1 => auxsc1487, i0 => auxsc1486); auxsc1488 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1488, i => auxsc352); auxsc1487 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1487, i2 => auxsc1471, i1 => auxsc1470, i0 => auxsc1469); auxsc1471 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1471, %0 A i2 => auxreg3, i1 => auxsc1454, i0 => auxsc1453); auxsc1454 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1454, i2 => auxsc39, i1 => auxsc1442, i0 => auxsc1444); auxsc1442 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1442, i1 => auxsc1441, i0 => auxsc1440); auxsc1441 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1441, i2 => auxsc1416, i1 => auxsc278, i0 => ir_opcod(2)); auxsc1416 : xr2_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1416, i1 => ir_opcod(3), i0 => ir_opcod(1)); a uxsc1440 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1440, i1 => auxsc1439, i0 => auxsc46); auxsc1439 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1439, i1 => ir_opcod(3), i0 => ir_opcod(0)); auxsc1444 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1444, i2 => auxsc1443, i1 => ir_opcod(13), i0 => ir_opcod(4)); auxsc1443 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1443, i1 => aux718_a, i0 => ir_opcod(5)); auxsc1453 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1 453, i1 => aux758_a, i0 => auxsc40); auxsc1470 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1470, i1 => auxsc6, i0 => auxsc27); auxsc1469 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1469, i1 => auxsc10, i0 => aux723_a); auxsc1486 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1486, i2 => auxsc27, i1 => auxsc1467, i0 => auxsc1466); auxsc1467 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1467, i1 => auxreg3, i0 => scout); auxsc1466 : a2_x2 PORT MAP ( vss => vss, vdd = > vdd, q => auxsc1466, i1 => auxsc1457, i0 => auxsc1456); auxsc1457 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1457, i1 => auxreg2, i0 => auxsc237); auxsc1456 : na3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1456, i2 => auxreg2, i1 => aux720_a, i0 => auxsc50); auxsc1485 : noa2a22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1485, i3 => auxsc1395, i2 => auxsc27, i1 => auxsc351, i0 => auxsc1459); auxsc1395 : nao2o22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1395, i3 => auxsc1224, i2 %3 D> auxsc1445, i1 => auxreg3, i0 => auxsc1446); auxsc1446 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1446, i1 => aux567_a, i0 => auxsc1445); auxsc1445 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1445, i1 => auxsc109, i0 => alu_sign); auxsc1459 : nxr2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1459, i1 => scout, i0 => auxsc109); auxsc1207 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1207, i1 => auxsc1295, i0 => auxsc1292); auxsc1295 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1295, i2 => auxsc456, i1 => auxsc1294, i0 => auxsc1293); auxsc1294 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1294, i1 => auxsc1289, i0 => frz); auxsc1289 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1289, i3 => auxsc1266, i2 => auxsc1265, i1 => auxsc1264, i0 => auxsc1261); auxsc1266 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1266, i2 => auxsc1251, i1 => auxsc1242, i0 => auxsc1240); auxsc1251 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1251, i2 => auxsc101 7, i1 => aux706_a, i0 => auxsc1250); auxsc1250 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1250, i => ir_opcod(9)); auxsc1242 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1242, i1 => auxsc1241, i0 => auxreg5); auxsc1241 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1241, i1 => auxsc1230, i0 => auxsc1229); auxsc1230 : oa2a22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1230, i3 => auxreg3, i2 => auxsc10, i1 => auxsc6, i0 => scout); auxsc1229 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1229, i2 => auxsc956, i1 => auxsc1228, i0 => ir_opcod(17)); auxsc1228 : na3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1228, i2 => aux699_a, i1 => auxsc21, i0 => ir_opcod(16)); auxsc1240 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1240, i2 => auxsc1227, i1 => auxsc1225, i0 => auxsc1223); auxsc1227 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1227, i2 => auxsc27, i1 => auxreg3, i0 => auxsc1221); auxsc1221 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => au xsc1221, i1 => scout, i0 => auxsc1128); auxsc1128 : oa2a22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1128, i3 => auxsc1102, i2 => auxsc1127, i1 => auxsc1123, i0 => auxsc36); auxsc1225 : no4_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1225, i3 => auxsc1224, i2 => ir_opcod(18), i1 => ir_opcod(17), i0 => ir_opcod(16)); auxsc1223 : no4_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1223, i3 => auxsc1222, i2 => ir_opcod(15), i1 => ir_opcod(14), i0 => ir_opcod(13)); auxsc1222 : ao2o22_x2 PORT MAP ( vss => v ss, vdd => vdd, q => auxsc1222, i3 => auxsc1216, i2 => auxsc1215, i1 => auxsc1214, i0 => ir_opcod(4)); auxsc1216 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1216, i1 => auxsc1213, i0 => auxsc1210); auxsc1213 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1213, i2 => ir_opcod(2), i1 => auxsc1212, i0 => auxsc1211); auxsc1212 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1212, i1 => auxsc45, i0 => ir_opcod(3)); auxsc1211 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1211, % 0A i2 => ir_opcod(0), i1 => auxsc45, i0 => ir_opcod(3)); auxsc1210 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1210, i2 => auxsc46, i1 => auxsc278, i0 => ir_opcod(3)); auxsc1215 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1215, i1 => auxsc515, i0 => ir_opcod(4)); auxsc1214 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1214, i2 => auxsc688, i1 => auxsc46, i0 => ir_opcod(5)); auxsc1265 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1265, i1 => auxsc171, i0 => auxsc423); %0 A auxsc1264 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1264, i1 => auxsc1263, i0 => auxsc1262); auxsc1263 : noa2a2a2a24_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1263, i7 => auxreg3, i6 => auxsc1237, i5 => auxsc6, i4 => auxsc1243, i3 => aux595_a, i2 => auxreg6, i1 => aux567_a, i0 => auxsc7); auxsc1237 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1237, i1 => auxreg2, i0 => auxsc1236); auxsc1236 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1236, i3 => auxsc10, i2 => auxsc1235, i1 => scout, i0 => adrs(1)); auxsc1235 : noa2a22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1235, i3 => auxsc1102, i2 => auxsc1127, i1 => auxsc1123, i0 => auxsc36); auxsc1102 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1102, i2 => auxsc1120, i1 => auxsc1115, i0 => auxsc1118); auxsc1120 : nao2o22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1120, i3 => auxsc1119, i2 => auxsc37, i1 => auxsc40, i0 => ir_opcod(13)); auxsc1115 : na3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1115, i2 %3 D> auxsc1114, i1 => auxsc1113, i0 => auxsc20); auxsc1114 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1114, i1 => auxsc1107, i0 => ir_opcod(4)); auxsc1107 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1107, i2 => auxsc857, i1 => auxsc688, i0 => ir_opcod(2)); auxsc1113 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1113, i1 => auxsc1105, i0 => ir_opcod(2)); auxsc1105 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1105, i2 => ir_opcod(3), i1 => ir_opcod(1), i0 => ir_opcod(0)); %0 A auxsc1118 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1118, i1 => auxsc1117, i0 => auxsc1116); auxsc1117 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1117, i1 => auxsc1110, i0 => auxsc1109); auxsc1110 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1110, i1 => ir_opcod(13), i0 => ir_opcod(5)); auxsc1109 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1109, i1 => ir_opcod(13), i0 => ir_opcod(6)); auxsc1127 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1127, i1 => auxsc108 7, i0 => auxsc50); auxsc1087 : nao2o22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1087, i3 => auxsc1119, i2 => auxsc37, i1 => ir_opcod(18), i0 => ir_opcod(16)); auxsc1123 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1123, i2 => auxsc1122, i1 => auxsc50, i0 => auxsc89); auxsc1122 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1122, i1 => ir_opcod(18), i0 => ir_opcod(16)); auxsc1243 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1243, i2 => scout, i1 => auxsc548, i0 => rqs);% 0D auxsc1262 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1262, i2 => auxsc352, i1 => auxsc1244, i0 => auxsc27); auxsc1244 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1244, i1 => auxreg2, i0 => auxsc7); auxsc1293 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1293, i2 => auxsc1287, i1 => auxsc1284, i0 => auxsc1282); auxsc1287 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1287, i1 => auxsc1286, i0 => auxsc1285); auxsc1286 : noa2a22_x1 PORT MAP ( vss => vss, vdd => vdd, nq =%3 E auxsc1286, i3 => auxsc1257, i2 => auxsc1276, i1 => aux576_a, i0 => auxsc352); auxsc1257 : nao2o22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1257, i3 => auxsc7, i2 => auxsc1256, i1 => auxsc1255, i0 => auxsc27); auxsc1256 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1256, i1 => auxsc1160, i0 => auxsc27); auxsc1160 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1160, i1 => auxsc1234, i0 => auxsc1232); auxsc1234 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1234, i2 => auxreg2, i1 => auxsc10, i0 => auxsc1233); auxsc1233 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1233, i2 => auxsc37, i1 => auxsc1217, i0 => ir_opcod(18)); auxsc1217 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1217, i1 => ir_opcod(17), i0 => ir_opcod(15)); auxsc1276 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1276, i1 => auxsc1254, i0 => auxreg5); auxsc1254 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1254, i1 => auxsc1253, i0 => rqs); auxsc1253 : nxr2_x1 PORT MAP ( vss => vss, v dd => vdd, nq => auxsc1253, i1 => scout, i0 => auxsc27); auxsc1284 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1284, i1 => auxsc1283, i0 => auxsc171); auxsc1283 : a3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1283, i2 => auxsc1280, i1 => auxsc1279, i0 => auxsc1278); auxsc1280 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1280, i2 => aux627_a, i1 => auxsc1271, i0 => auxsc1270); auxsc1271 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1271, i1 => auxsc1131, i0 => auxreg6); auxsc1 131 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1131, i1 => auxsc10, i0 => auxreg2); auxsc1279 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1279, i2 => auxsc106, i1 => scout, i0 => auxsc1273); auxsc1273 : na4_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1273, i3 => aux696_a, i2 => auxsc352, i1 => auxsc234, i0 => auxreg4); auxsc1278 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1278, i1 => scout, i0 => auxsc27); auxsc1282 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q =% 3E auxsc1282, i1 => frz, i0 => auxsc423); auxsc1292 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1292, i1 => auxsc454, i0 => auxsc352); auxsc970 : nao2o22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc970, i3 => auxsc1066, i2 => auxsc456, i1 => auxsc454, i0 => auxsc423); auxsc1066 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1066, i2 => auxsc1064, i1 => auxsc1063, i0 => auxsc128); auxsc1064 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1064, i2 => auxsc128, i1 => auxsc792, i0 => auxsc7); auxsc1063 : o4_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1063, i3 => auxsc1056, i2 => auxsc1059, i1 => auxsc1053, i0 => auxsc1050); auxsc1056 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1056, i2 => auxreg7, i1 => auxsc1055, i0 => auxsc1054); auxsc1055 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1055, i2 => auxreg4, i1 => auxsc1042, i0 => auxsc1043); auxsc1042 : o4_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1042, i3 => auxsc1014, i2 => auxsc1011, i1 => auxsc1012, i0 => auxsc1013); auxsc1014 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1014, i1 => auxsc1002, i0 => auxreg5); auxsc1002 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1002, i1 => auxreg2, i0 => auxreg6); auxsc1011 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1011, i1 => auxsc933, i0 => auxsc7); auxsc933 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc933, i1 => scout, i0 => auxsc988); auxsc988 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc988, i1 => auxsc984, i0 => auxsc981); auxsc984 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc984, i2 => ir_opcod(15), i1 => auxsc983, i0 => auxsc982); auxsc983 : nao2o22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc983, i3 => auxsc974, i2 => ir_opcod(3), i1 => auxsc972, i0 => auxsc973); auxsc974 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc974, i1 => auxsc46, i0 => auxsc278); auxsc972 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc972, i1 => auxsc47, i0 => ir_opcod(0)); auxsc973 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc973, i1 => aux712_a, i0 => ir_opcod(2)); auxsc982 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc982, i2 => auxsc515, i1 => ir_opcod(13), i0 => ir_opcod(4)); auxsc981 : a4_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc981, i3 => auxsc21, i2 => auxsc50, i1 => auxsc37, i0 => auxsc40); auxsc1012 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1012, i1 => auxsc10, i0 => aux713_a); auxsc1013 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1013, i1 => aux603_a, i0 => itrqs); auxsc1043 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1043, i2 => auxsc1017, i1 => auxsc1016, i0 => ir_opcod(9)); auxsc1017 : na3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1017, i2 => aux570_a, i1 => auxsc27, i0 => auxreg5); auxsc1016 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1016, i2 => auxsc909, i1 => scout, i0 => ir_opcod(10)); auxsc909 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc909, i1 => ir_opcod(10), i0 => ir_opcod(8)); auxsc10 54 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1054, i2 => auxsc1040, i1 => auxsc1026, i0 => auxsc1027); auxsc1040 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1040, i2 => auxsc1039, i1 => scout, i0 => rqs); auxsc1039 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1039, i1 => auxsc1028, i0 => auxreg6); auxsc1026 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1026, i2 => auxsc7, i1 => auxsc1019, i0 => auxsc956); auxsc1019 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q % 3D> auxsc1019, i1 => auxreg2, i0 => auxsc989); auxsc989 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc989, i1 => scout, i0 => auxsc978); auxsc978 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc978, i2 => auxsc284, i1 => aux687_a, i0 => auxsc895); auxsc895 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc895, i1 => ir_opcod(15), i0 => ir_opcod(13)); auxsc1027 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1027, i1 => auxsc14, i0 => auxreg3); auxsc1059 : noa22_x1 PORT MAP ( vss =%3 E vss, vdd => vdd, nq => auxsc1059, i2 => auxsc171, i1 => auxsc1058, i0 => auxsc1057); auxsc1058 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1058, i1 => auxsc1034, i0 => auxsc1031); auxsc1034 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1034, i2 => auxsc1033, i1 => auxsc1032, i0 => auxsc423); auxsc1033 : noa2a2a23_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1033, i5 => auxsc14, i4 => auxsc7, i3 => aux578_a, i2 => auxreg3, i1 => auxreg2, i0 => auxsc998); auxsc998 : a2_x2 PORT MAP ( vss % 3D> vss, vdd => vdd, q => auxsc998, i1 => auxsc548, i0 => auxsc234); auxsc548 : na3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc548, i2 => aux677_a, i1 => auxsc543, i0 => auxsc39); auxsc1032 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1032, i2 => auxsc352, i1 => aux590_a, i0 => auxsc1023); auxsc1023 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1023, i1 => auxsc691, i0 => auxsc716); auxsc1031 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1031, i1 => auxsc27, i0 => scout) ; auxsc1057 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1057, i2 => auxsc1037, i1 => auxsc1035, i0 => auxsc1036); auxsc1037 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1037, i1 => auxsc423, i0 => auxreg5); auxsc1035 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1035, i1 => auxsc1006, i0 => auxsc1005); auxsc1005 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1005, i2 => auxsc14, i1 => auxsc1004, i0 => rqs); auxsc1004 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1004, i2 => auxsc697, i1 => auxsc698, i0 => ir_opcod(15)); auxsc1036 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1036, i2 => auxsc1007, i1 => auxsc1008, i0 => auxsc7); auxsc1007 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1007, i1 => auxsc959, i0 => auxsc10); auxsc959 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc959, i1 => auxreg2, i0 => auxsc987); auxsc987 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc987, i1 => auxsc986, i0 => auxsc985); auxsc986 : oa22_x2 PORT MAP %2 8 vss => vss, vdd => vdd, q => auxsc986, i2 => ir_opcod(17), i1 => auxsc878, i0 => auxsc877); auxsc985 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc985, i2 => auxsc23, i1 => auxsc92, i0 => auxsc50); auxsc1008 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1008, i1 => aux587_a, i0 => adrs(1)); auxsc1053 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1053, i1 => auxsc1052, i0 => auxsc1051); auxsc1052 : noa2a22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1052, i3 => auxsc6, i2 => auxreg3, i1 => auxreg2, i0 => scout); auxsc1051 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1051, i1 => auxsc1046, i0 => auxsc27); auxsc1050 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1050, i2 => auxsc1049, i1 => auxsc1028, i0 => rqs); auxsc1049 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1049, i1 => aux583_a, i0 => auxreg6); auxsc666 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc666, i1 => auxsc801, i0 => auxsc798); auxsc801 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc801, i2 => auxsc456, i1 => auxsc800, i0 => auxsc799); auxsc800 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc800, i2 => frz, i1 => auxsc795, i0 => auxsc794); auxsc795 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc795, i2 => auxsc171, i1 => auxsc790, i0 => auxsc789); auxsc790 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc790, i2 => auxreg4, i1 => auxsc779, i0 => auxsc778); auxsc779 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc779, i1 => a uxsc759, i0 => auxreg5); auxsc759 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc759, i3 => auxsc721, i2 => rqs, i1 => auxsc703, i0 => auxsc27); auxsc721 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc721, i1 => aux591_a, i0 => auxsc27); auxsc778 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc778, i2 => auxsc352, i1 => auxsc757, i0 => auxsc756); auxsc757 : nao2o22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc757, i3 => auxsc704, i2 => auxsc715, i1 => auxsc10, i0 => auxsc692)%3 B auxsc704 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc704, i1 => auxsc696, i0 => auxsc7); auxsc696 : on12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc696, i1 => auxsc695, i0 => auxsc694); auxsc695 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc695, i2 => scout, i1 => auxsc536, i0 => auxsc677); auxsc677 : na3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc677, i2 => auxsc670, i1 => auxsc669, i0 => auxsc668); auxsc670 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc670, %0 A i1 => auxsc532, i0 => ir_opcod(16)); auxsc669 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc669, i1 => auxsc530, i0 => auxsc37); auxsc668 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc668, i2 => auxsc50, i1 => auxsc528, i0 => ir_opcod(12)); auxsc694 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc694, i2 => auxsc693, i1 => scout, i0 => adrs(1)); auxsc693 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc693, i1 => auxsc692, i0 => auxsc691); auxsc691 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc691, i => adrs(1)); auxsc715 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc715, i1 => auxsc703, i0 => auxreg6); auxsc756 : na4_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc756, i3 => auxsc10, i2 => aux696_a, i1 => auxsc234, i0 => auxsc6); auxsc789 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc789, i2 => auxsc423, i1 => auxsc776, i0 => auxsc775); auxsc776 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc776, i1 => auxsc763, i0 => auxreg5); % 0A auxsc763 : noa2a2a2a24_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc763, i7 => auxsc10, i6 => auxreg6, i5 => auxsc724, i4 => auxreg3, i3 => auxsc723, i2 => auxsc692, i1 => auxsc629, i0 => aux671_a); auxsc724 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc724, i1 => scout, i0 => auxreg2); auxsc723 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc723, i1 => auxsc722, i0 => rqs); auxsc722 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc722, i2 => auxsc27, i1 => auxsc705, i0 => aux sc7); auxsc705 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc705, i2 => auxsc698, i1 => auxsc697, i0 => ir_opcod(15)); auxsc698 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc698, i1 => auxsc40, i0 => ir_opcod(13)); auxsc697 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc697, i1 => aux757_a, i0 => ir_opcod(18)); auxsc692 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc692, i => auxsc6); auxsc629 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc629, i1 => auxsc543, %0 A i0 => auxsc36); auxsc775 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc775, i2 => auxsc622, i1 => auxsc761, i0 => auxsc352); auxsc622 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc622, i1 => aux567_a, i0 => auxsc621); auxsc761 : a3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc761, i2 => auxsc741, i1 => auxsc621, i0 => auxsc7); auxsc741 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc741, i1 => scout, i0 => auxsc717); auxsc717 : nxr2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc717, i1 => auxsc716, i0 => adrs(1)); auxsc716 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc716, i => adrs(0)); auxsc621 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc621, i2 => auxsc27, i1 => scout, i0 => auxsc7); auxsc794 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc794, i2 => auxreg7, i1 => auxsc787, i0 => auxsc786); auxsc787 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc787, i1 => auxsc784, i0 => auxsc423); auxsc784 : noa2a22_x1 PORT MAP ( vss => vss, % 0A vdd => vdd, nq => auxsc784, i3 => auxsc773, i2 => auxsc755, i1 => auxsc557, i0 => auxsc352); auxsc773 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc773, i1 => auxsc752, i0 => auxsc753); auxsc752 : oa2a22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc752, i3 => auxsc751, i2 => auxsc7, i1 => auxsc750, i0 => auxreg3); auxsc751 : xr2_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc751, i1 => scout, i0 => auxreg2); auxsc750 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc750, i2 => scout , i1 => auxsc564, i0 => auxsc6); auxsc564 : na3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc564, i2 => auxsc83, i1 => auxsc690, i0 => auxsc284); auxsc753 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc753, i2 => auxsc352, i1 => auxsc585, i0 => auxreg6); auxsc585 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc585, i1 => scout, i0 => auxreg2); auxsc755 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc755, i1 => auxsc754, i0 => rqs); auxsc557 : nao2o22_x1 PORT MAP ( vss => vs s, vdd => vdd, nq => auxsc557, i3 => auxsc383, i2 => auxsc740, i1 => auxsc739, i0 => auxreg6); auxsc740 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc740, i1 => auxsc234, i0 => auxreg6); auxsc786 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc786, i2 => auxreg4, i1 => auxsc781, i0 => auxsc782); auxsc781 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc781, i2 => auxsc767, i1 => auxsc768, i0 => auxreg5); auxsc767 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc767, i1 %3 D> auxsc727, i0 => auxsc731); auxsc727 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc727, i2 => auxsc27, i1 => auxsc726, i0 => auxsc725); auxsc726 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc726, i1 => scout, i0 => auxreg3); auxsc725 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc725, i2 => auxsc702, i1 => scout, i0 => auxreg2); auxsc702 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc702, i2 => auxsc7, i1 => auxsc701, i0 => auxsc590); auxsc701 : o3_x2 PORT MAP ( v ss => vss, vdd => vdd, q => auxsc701, i2 => auxsc39, i1 => auxsc311, i0 => auxsc6); auxsc590 : na3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc590, i2 => auxsc21, i1 => auxsc50, i0 => ir_opcod(16)); auxsc731 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc731, i2 => auxsc730, i1 => auxsc729, i0 => auxsc728); auxsc730 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc730, i1 => scout, i0 => auxsc706); auxsc706 : no4_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc706, i3 => auxsc536, i2 => auxsc533, i1 => auxsc531, i0 => auxsc529); auxsc536 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc536, i2 => auxsc503, i1 => auxsc535, i0 => auxsc534); auxsc503 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc503, i1 => auxsc512, i0 => ir_opcod(5)); auxsc512 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc512, i1 => auxsc511, i0 => ir_opcod(4)); auxsc511 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc511, i2 => ir_opcod(3), i1 => auxsc45, i0 => ir_opcod(2)); auxs c535 : a4_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc535, i3 => auxsc523, i2 => auxsc522, i1 => auxsc515, i0 => auxsc63); auxsc523 : xr2_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc523, i1 => auxsc510, i0 => auxsc47); auxsc510 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc510, i1 => auxsc278, i0 => ir_opcod(1)); auxsc522 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc522, i1 => auxsc46, i0 => auxsc45); auxsc534 : o4_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc534, i3 => auxsc520, i2 => auxsc22, i1 => ir_opcod(15), i0 => ir_opcod(13)); auxsc520 : no4_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc520, i3 => auxsc500, i2 => auxsc501, i1 => auxsc63, i0 => ir_opcod(5)); auxsc501 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc501, i1 => ir_opcod(1), i0 => ir_opcod(0)); auxsc533 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc533, i1 => auxsc532, i0 => ir_opcod(16)); auxsc532 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc532, i2 => auxsc44, i1 => auxsc517, i0 => ir_opcod(18)); auxsc517 : no4_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc517, i3 => auxsc24, i2 => auxsc20, i1 => auxsc76, i0 => ir_opcod(6)); auxsc531 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc531, i1 => auxsc530, i0 => auxsc37); auxsc530 : noa2a22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc530, i3 => auxsc105, i2 => ir_opcod(15), i1 => ir_opcod(18), i0 => ir_opcod(14)); auxsc529 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc529, i2 => auxsc50, i1 => auxsc528, i0 => ir_opcod(12)); auxsc528 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc528, i2 => ir_opcod(16), i1 => ir_opcod(15), i0 => ir_opcod(13)); auxsc729 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc729, i2 => auxreg3, i1 => scout, i0 => auxsc700); auxsc700 : no4_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc700, i3 => auxsc686, i2 => auxsc687, i1 => auxsc689, i0 => auxsc681); auxsc686 : na4_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc686, i3 => auxsc685, i2 => auxsc 684, i1 => auxsc683, i0 => auxsc682); auxsc685 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc685, i1 => auxsc47, i0 => auxsc46); auxsc684 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc684, i1 => auxsc47, i0 => ir_opcod(0)); auxsc683 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc683, i1 => auxsc278, i0 => ir_opcod(1)); auxsc682 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc682, i2 => ir_opcod(5), i1 => auxsc47, i0 => ir_opcod(1)); auxsc687 : na2_x1 PORT MAP ( vss => vss%2 C vdd => vdd, nq => auxsc687, i1 => aux672_a, i0 => auxsc63); auxsc689 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc689, i1 => auxsc688, i0 => ir_opcod(2)); auxsc688 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc688, i1 => auxsc47, i0 => ir_opcod(1)); auxsc681 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc681, i1 => aux757_a, i0 => auxsc21); auxsc768 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc768, i1 => auxsc732, i0 => itrqs); auxsc732 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc732, i1 => aux603_a, i0 => auxsc27); auxsc782 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc782, i2 => auxsc765, i1 => aux623_a, i0 => auxsc352); auxsc765 : a4_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc765, i3 => auxsc748, i2 => auxsc747, i1 => auxsc746, i0 => auxsc745); auxsc748 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc748, i1 => auxsc14, i0 => auxsc7); auxsc747 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc747, i2 => auxsc735, i1 => auxsc734, i0 => auxsc106); auxsc735 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc735, i1 => scout, i0 => auxsc472); auxsc734 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc734, i2 => scout, i1 => auxsc712, i0 => ir_opcod(9)); auxsc712 : nxr2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc712, i1 => auxsc711, i0 => ir_opcod(10)); auxsc711 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc711, i => ir_opcod(8)); auxsc746 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc74 6, i1 => auxsc106, i0 => auxsc27); auxsc799 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc799, i2 => auxsc128, i1 => auxsc792, i0 => auxsc6); auxsc792 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc792, i1 => aux633_a, i0 => auxreg7); auxsc798 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc798, i1 => auxsc454, i0 => auxsc7); auxsc276 : noa2a22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc276, i3 => auxsc463, i2 => auxsc462, i1 => auxsc6, i0 => test); auxsc463 : oa22_x2 POR T MAP ( vss => vss, vdd => vdd, q => auxsc463, i2 => frz, i1 => auxsc460, i0 => auxsc459); auxsc460 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc460, i2 => auxreg7, i1 => auxsc449, i0 => auxsc448); auxsc449 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc449, i2 => auxreg4, i1 => auxsc431, i0 => auxsc430); auxsc431 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc431, i2 => auxreg5, i1 => auxsc401, i0 => auxsc400); auxsc401 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq %3 D> auxsc401, i2 => auxsc357, i1 => auxsc334, i0 => auxsc331); auxsc357 : na4_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc357, i3 => auxsc344, i2 => auxsc343, i1 => auxsc27, i0 => rqs); auxsc344 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc344, i1 => aux578_a, i0 => auxreg3); auxsc334 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc334, i2 => auxreg6, i1 => auxsc333, i0 => auxsc332); auxsc333 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc333, i2 => auxsc10, i1 => auxsc317, i0 => auxsc6); auxsc332 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc332, i1 => auxsc315, i0 => auxsc7); auxsc315 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc315, i2 => auxsc306, i1 => auxsc292, i0 => auxsc290); auxsc306 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc306, i1 => scout, i0 => auxreg2); auxsc292 : oa2a22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc292, i3 => auxsc291, i2 => auxsc255, i1 => auxsc282, i0 => ir_opcod(15)); auxsc291 : a3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc291, i2 => aux672_a, i1 => auxsc63, i0 => auxsc251); auxsc251 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc251, i2 => ir_opcod(5), i1 => ir_opcod(2), i0 => ir_opcod(0)); auxsc255 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc255, i1 => auxsc281, i0 => auxsc280); auxsc281 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc281, i1 => auxsc45, i0 => ir_opcod(3)); auxsc280 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc280, i1 => auxsc279, i0 % 3D> auxsc278); auxsc279 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc279, i1 => ir_opcod(3), i0 => ir_opcod(2)); auxsc282 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc282, i1 => auxsc20, i0 => ir_opcod(14)); auxsc290 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc290, i1 => auxsc22, i0 => ir_opcod(18)); auxsc331 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc331, i1 => auxsc330, i0 => auxsc27); auxsc330 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc330, i2 % 3D> auxsc326, i1 => auxsc319, i0 => auxreg3); auxsc326 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc326, i1 => auxsc7, i0 => scout); auxsc319 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc319, i3 => auxsc301, i2 => auxsc6, i1 => aux685_a, i0 => auxsc14); auxsc301 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc301, i2 => scout, i1 => auxsc285, i0 => auxsc284); auxsc285 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc285, i1 => auxsc74, i0 => auxsc39); auxsc284 : an12_x1 % 0A PORT MAP ( vss => vss, vdd => vdd, q => auxsc284, i1 => auxsc283, i0 => auxsc37); auxsc283 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc283, i1 => ir_opcod(18), i0 => ir_opcod(17)); auxsc400 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc400, i1 => auxsc355, i0 => auxsc354); auxsc355 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc355, i1 => auxsc348, i0 => auxreg6); auxsc354 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc354, i => itrqs); auxsc430 : o2_x2 PORT MAP ( %0 A vss => vss, vdd => vdd, q => auxsc430, i1 => auxsc398, i0 => auxsc352); auxsc398 : noa2a2a23_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc398, i5 => auxsc228, i4 => auxsc27, i3 => auxsc209, i2 => auxsc234, i1 => auxsc351, i0 => auxsc350); auxsc228 : nao2o22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc228, i3 => auxsc336, i2 => auxsc7, i1 => auxsc335, i0 => auxreg3); auxsc336 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc336, i2 => auxsc328, i1 => auxsc309, i0 => auxreg2); auxsc328 : noa22 _x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc328, i2 => auxsc14, i1 => auxsc109, i0 => alu_sign); auxsc109 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc109, i => resnul); auxsc309 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc309, i2 => auxsc308, i1 => auxsc303, i0 => ir_opcod(8)); auxsc308 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc308, i2 => ir_opcod(9), i1 => ir_opcod(8), i0 => auxsc10); auxsc303 : na3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc303, i2 => ir_opcod(10), i1 => ir_opcod(9), i0 => auxsc10); auxsc335 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc335, i2 => aux567_a, i1 => auxsc304, i0 => resnul); auxsc304 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc304, i => alu_sign); auxsc209 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc209, i2 => auxsc337, i1 => aux570_a, i0 => auxsc27); auxsc234 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc234, i => rqs); auxsc351 : no2_x1 PORT MAP ( vss => vss, vdd => vdd , nq => auxsc351, i1 => auxsc106, i0 => auxsc27); auxsc350 : nxr2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc350, i1 => resnul, i0 => scout); auxsc448 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc448, i2 => auxsc423, i1 => auxsc428, i0 => auxsc427); auxsc428 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc428, i2 => auxsc352, i1 => auxsc407, i0 => auxsc406); auxsc407 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc407, i2 => auxreg6, i1 => auxsc362, i0 => auxsc361); a uxsc362 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc362, i2 => auxsc7, i1 => auxsc340, i0 => auxsc339); auxsc340 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc340, i2 => auxsc324, i1 => aux699_a, i0 => auxsc323); auxsc324 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc324, i2 => auxsc14, i1 => auxsc313, i0 => auxsc37); auxsc323 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc323, i1 => auxsc311, i0 => auxsc39); auxsc311 : nxr2_x1 PORT MAP ( vss => vss, vdd => vdd, nq =%3 E auxsc311, i1 => ir_opcod(14), i0 => ir_opcod(13)); auxsc339 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc339, i2 => auxsc237, i1 => auxsc6, i0 => auxsc10); auxsc237 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc237, i1 => resnul, i0 => alu_sign); auxsc361 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc361, i1 => aux578_a, i0 => auxreg3); auxsc406 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc406, i1 => auxsc359, i0 => rqs); auxsc359 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc359, i3 => aux570_a, i2 => auxsc10, i1 => auxsc27, i0 => scout); auxsc427 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc427, i2 => auxreg5, i1 => auxsc404, i0 => auxsc403); auxsc404 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc404, i2 => rqs, i1 => auxsc365, i0 => auxsc366); auxsc365 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc365, i2 => auxreg6, i1 => auxsc213, i0 => auxreg3); auxsc366 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc366, % 0A i1 => auxsc27, i0 => auxsc7); auxsc403 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc403, i2 => aux569_a, i1 => auxreg6, i0 => auxsc10); auxsc459 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc459, i1 => auxsc446, i0 => auxsc171); auxsc446 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc446, i2 => auxsc442, i1 => auxsc167, i0 => auxsc441); auxsc442 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc442, i2 => auxsc423, i1 => auxsc437, i0 => auxsc436); auxsc437 : o3_x2 PORT MAP % 28 vss => vss, vdd => vdd, q => auxsc437, i2 => auxsc421, i1 => auxsc420, i0 => rqs); auxsc421 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc421, i2 => auxsc370, i1 => auxsc368, i0 => auxreg5); auxsc370 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc370, i1 => auxsc369, i0 => auxreg6); auxsc369 : nxr2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc369, i1 => auxsc7, i0 => auxsc14); auxsc368 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc368, i1 => auxsc27, i0 => auxreg 2); auxsc420 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc420, i1 => auxsc139, i0 => auxsc10); auxsc139 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc139, i1 => auxsc352, i0 => auxreg6); auxsc436 : a4_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc436, i3 => auxsc418, i2 => auxsc417, i1 => auxsc416, i0 => auxsc415); auxsc418 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc418, i2 => auxsc396, i1 => auxsc395, i0 => auxreg5); auxsc396 : no3_x1 PORT MAP ( vss => vss, vdd => vdd,% 0D nq => auxsc396, i2 => auxsc23, i1 => auxsc21, i0 => auxsc22); auxsc395 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc395, i1 => auxsc7, i0 => auxsc14); auxsc417 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc417, i2 => auxsc7, i1 => auxsc393, i0 => auxsc391); auxsc393 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc393, i1 => auxsc392, i0 => auxsc352); auxsc391 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc391, i2 => auxsc14, i1 => auxsc36, i0 => auxsc372); auxsc36 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc36, i1 => auxsc24, i0 => ir_opcod(13)); auxsc372 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc372, i1 => auxsc21, i0 => auxsc22); auxsc22 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc22, i1 => ir_opcod(17), i0 => ir_opcod(16)); auxsc416 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc416, i1 => auxsc27, i0 => scout); auxsc415 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc415, i1 => auxsc389, i0 => auxreg5); auxsc389 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc389, i2 => auxreg2, i1 => adrs(0), i0 => scout); auxsc167 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc167, i2 => auxsc412, i1 => auxsc317, i0 => auxsc409); auxsc412 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc412, i1 => auxsc411, i0 => auxsc410); auxsc411 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc411, i1 => auxsc385, i0 => rqs); auxsc385 : noa2a22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc385, i3 => auxsc6, i2 => auxreg6, i1 => auxsc27, i0 => auxsc7); auxsc410 : a4_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc410, i3 => auxsc383, i2 => auxsc382, i1 => auxsc381, i0 => auxreg5); auxsc383 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc383, i1 => aux567_a, i0 => auxsc7); auxsc382 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc382, i1 => aux582_a, i0 => auxreg3); auxsc381 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc381, i2 => auxreg6, i1 => auxsc160, i0 => auxsc10) ; auxsc160 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc160, i1 => resnul, i0 => auxreg2); auxsc317 : noa2a22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc317, i3 => auxsc297, i2 => auxsc296, i1 => auxsc295, i0 => auxsc294); auxsc297 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc297, i2 => auxsc87, i1 => auxsc84, i0 => auxsc81); auxsc87 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc87, i2 => auxsc86, i1 => auxsc85, i0 => ir_opcod(18)); auxsc86 : ao2o22_x2 PORT MAP ( vss =%3 E vss, vdd => vdd, q => auxsc86, i3 => auxsc75, i2 => ir_opcod(5), i1 => auxsc74, i0 => auxsc39); auxsc75 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc75, i1 => aux762_a, i0 => auxsc20); auxsc85 : noa2a2a2a24_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc85, i7 => auxsc73, i6 => ir_opcod(0), i5 => aux681_a, i4 => auxsc72, i3 => aux765_a, i2 => auxsc45, i1 => auxsc44, i0 => ir_opcod(15)); auxsc73 : a3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc73, i2 => auxsc47, i1 => auxsc46, i0 => ir_opcod(1)); auxsc72 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc72, i1 => auxsc63, i0 => auxsc46); auxsc44 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc44, i1 => auxsc40, i0 => ir_opcod(13)); auxsc84 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc84, i1 => auxsc83, i0 => auxsc82); auxsc83 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc83, i1 => auxsc20, i0 => ir_opcod(15)); auxsc82 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc82, i1 => auxsc40, % 0A i0 => auxsc76); auxsc76 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc76, i => ir_opcod(7)); auxsc81 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc81, i1 => auxsc80, i0 => auxsc21); auxsc80 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc80, i1 => auxsc20, i0 => ir_opcod(14)); auxsc296 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc296, i1 => auxsc52, i0 => auxsc50); auxsc52 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc52, i1 => aux676_a, i0 => auxsc37); % 0A auxsc294 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc294, i1 => auxsc89, i0 => auxsc88); auxsc89 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc89, i => ir_opcod(12)); auxsc88 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc88, i => ir_opcod(11)); auxsc409 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc409, i1 => auxsc213, i0 => auxsc7); auxsc441 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc441, i1 => auxsc433, i0 => auxreg4); auxsc433 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc433, i2 => auxsc414, i1 => auxsc413, i0 => auxreg5); auxsc414 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc414, i1 => auxsc154, i0 => auxsc27); auxsc154 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc154, i2 => scout, i1 => auxsc6, i0 => auxreg3); auxsc413 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc413, i2 => rqs, i1 => auxsc7, i0 => auxreg6); auxsc462 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc462, i1 => auxsc458, i0 => auxsc456); auxsc458 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc458, i1 => auxsc457, i0 => auxsc128); auxsc457 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc457, i2 => auxsc452, i1 => auxsc123, i0 => auxsc451); auxsc452 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc452, i1 => auxreg7, i0 => auxsc10); auxsc123 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc123, i1 => auxsc426, i0 => auxsc424); auxsc426 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc426, i1 => auxsc425, i0 => auxsc27); auxsc424 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc424, i1 => auxsc352, i0 => auxsc423); auxsc451 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc451, i1 => auxsc444, i0 => auxreg7); auxsc444 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc444, i1 => auxsc27, i0 => auxsc10); auxsc456 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc456, i1 => auxsc455, i0 => auxsc454); auxsc2855 : a3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2855, i2 % 3D> auxsc27, i1 => auxreg5, i0 => aux626_a); auxsc2848 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2848, i1 => aux742_a, i0 => aux626_a); auxsc2854 : oa2a22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2854, i3 => aux738_a, i2 => auxsc2853, i1 => auxsc1975, i0 => auxsc2137); auxsc2853 : xr2_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2853, i1 => auxreg3, i0 => auxsc14); auxsc2847 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2847, i2 => auxreg7, i1 => auxsc2842, i0 => auxsc2841); aux sc2842 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2842, i1 => auxsc2795, i0 => auxsc423); auxsc2795 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2795, i1 => auxreg6, i0 => auxsc2834); auxsc2834 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2834, i1 => auxreg5, i0 => aux578_a); auxsc2841 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2841, i2 => auxsc423, i1 => auxsc2840, i0 => auxsc2839); auxsc2840 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2840, i2 => auxsc352% 2C i1 => auxreg6, i0 => auxsc1957); auxsc2839 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2839, i2 => auxreg5, i1 => auxreg6, i0 => auxsc2826); auxsc2826 : nxr2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2826, i1 => auxreg3, i0 => aux567_a); auxsc2843 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2843, i3 => auxsc2838, i2 => auxsc423, i1 => auxsc2837, i0 => auxreg4); auxsc2838 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2838, i2 => auxsc2835, i1 => auxsc2829, i0 => auxs c352); auxsc2835 : na3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2835, i2 => auxsc27, i1 => auxsc352, i0 => aux615_a); auxsc2829 : noa2a22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2829, i3 => auxsc27, i2 => aux595_a, i1 => auxreg6, i0 => auxsc2109); auxsc2837 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2837, i3 => auxsc2025, i2 => auxsc2831, i1 => auxreg6, i0 => auxsc2830); auxsc2831 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2831, i1 => auxreg3, i0 => auxsc2511); auxsc2830 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2830, i1 => auxsc352, i0 => auxsc1709); auxsc2790 : nao2o22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2790, i3 => auxreg6, i2 => auxsc2578, i1 => auxreg3, i0 => auxsc956); auxsc2786 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2786, i3 => auxsc2785, i2 => auxreg4, i1 => auxreg6, i0 => auxsc2784); auxsc2785 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2785, i1 => auxsc2310, i0 => auxreg5); auxsc2784 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2784, i1 => aux738_a, i0 => aux605_a); auxsc2773 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2773, i1 => auxreg7, i0 => auxsc2772); auxsc2772 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2772, i3 => auxsc2771, i2 => auxreg4, i1 => auxsc352, i0 => auxsc1626); auxsc2771 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2771, i3 => auxsc2620, i2 => auxreg5, i1 => auxsc2755, i0 => auxsc352); auxsc2755 : noa2a22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2 755, i3 => auxreg6, i2 => auxsc2210, i1 => auxreg3, i0 => aux578_a); auxsc2770 : on12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2770, i1 => auxreg7, i0 => auxsc2769); auxsc2769 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2769, i3 => auxsc2768, i2 => auxreg4, i1 => auxsc2763, i0 => auxsc2765); auxsc2768 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2768, i1 => auxsc2767, i0 => auxsc2766); auxsc2767 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2767, i2 => auxsc2757, i1 => au xreg6, i0 => auxsc2144); auxsc2757 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2757, i2 => auxreg5, i1 => auxsc7, i0 => auxsc8); auxsc2766 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2766, i2 => auxsc2756, i1 => auxreg6, i0 => auxsc1651); auxsc2756 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2756, i2 => auxsc352, i1 => auxreg3, i0 => auxsc8); auxsc2763 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2763, i1 => auxsc27, i0 => aux736_a); auxsc2765 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2765, i1 => auxreg3, i0 => aux587_a); auxsc2734 : nao2o22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2734, i3 => auxreg7, i2 => auxsc2733, i1 => auxsc2731, i0 => auxsc423); auxsc2733 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2733, i1 => auxsc2732, i0 => auxsc2719); auxsc2732 : o4_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2732, i3 => auxsc2716, i2 => auxsc2715, i1 => auxreg4, i0 => auxsc2713); auxsc2716 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq % 3D> auxsc2716, i1 => auxsc2270, i0 => auxsc14); auxsc2715 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2715, i1 => auxreg5, i0 => auxsc2714); auxsc2714 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2714, i => auxsc703); auxsc2713 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2713, i1 => auxsc14, i0 => auxsc7); auxsc2719 : on12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2719, i1 => auxsc2712, i0 => auxsc2710); auxsc2712 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2712%2 C i2 => auxreg4, i1 => auxreg6, i0 => auxsc2711); auxsc2711 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2711, i1 => auxreg5, i0 => aux570_a); auxsc2710 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2710, i1 => auxreg5, i0 => auxsc1801); auxsc2731 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2731, i1 => auxsc2730, i0 => auxsc2729); auxsc2730 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2730, i1 => aux731_a, i0 => auxsc2072); auxsc2729 : a3_x2 PORT MAP ( vss => vss, vdd =%3 E vdd, q => auxsc2729, i2 => auxsc2253, i1 => auxreg5, i0 => auxsc1846); auxsc2728 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2728, i1 => auxreg7, i0 => auxsc2727); auxsc2727 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2727, i3 => auxsc1046, i2 => auxsc2675, i1 => auxsc1028, i0 => auxsc2721); auxsc2721 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2721, i1 => auxsc7, i0 => auxreg2); auxsc2726 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2726, i2 => auxsc2725, i1 => a ux775_a, i0 => auxreg4); auxsc2725 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2725, i2 => auxsc1891, i1 => auxsc2697, i0 => auxreg5); auxsc2697 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2697, i2 => auxsc2709, i1 => auxreg6, i0 => auxreg3); auxsc2709 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2709, i1 => auxsc10, i0 => auxsc6); auxsc2684 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2684, i1 => auxsc2682, i0 => auxsc2681); auxsc2682 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2682, i2 => aux633_a, i1 => auxsc2672, i0 => auxsc1046); auxsc2672 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2672, i1 => auxreg6, i0 => auxsc2675); auxsc2675 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2675, i1 => auxreg3, i0 => auxsc14); auxsc2681 : oa2a2a23_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2681, i5 => auxsc2680, i4 => auxsc2679, i3 => auxsc1975, i2 => auxsc2678, i1 => auxreg4, i0 => auxsc6); auxsc2680 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2680, i1 => auxreg5, i0 => auxreg3); auxsc2679 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2679, i1 => auxsc423, i0 => scout); auxsc2678 : oa2a22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2678, i3 => auxreg3, i2 => auxreg2, i1 => auxreg2, i0 => auxsc10); auxsc2657 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2657, i1 => aux731_a, i0 => auxsc2676); auxsc2676 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2676, i1 => auxreg3, i0 => aux582_a); auxsc2683 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2683, i1 => aux729_a, i0 => aux569_a); auxsc2649 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2649, i2 => auxsc171, i1 => auxreg5, i0 => auxsc423); auxsc2648 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2648, i1 => auxsc7, i0 => scout); auxsc2647 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2647, i1 => auxsc27, i0 => aux601_a); auxsc2642 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2642, i1 => auxsc171, i0 => auxsc10); au xsc1285 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1285, i1 => auxreg7, i0 => auxsc423); auxsc2641 : na3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2641, i2 => auxsc27, i1 => auxsc352, i0 => auxsc1322); auxsc2636 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2636, i1 => auxreg7, i0 => auxsc2635); auxsc2635 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2635, i2 => auxsc2633, i1 => auxsc2631, i0 => auxsc1732); auxsc2633 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2633,% 0D i1 => auxsc2071, i0 => auxsc2144); auxsc2631 : noa2a2a23_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2631, i5 => auxreg6, i4 => auxsc2210, i3 => auxreg3, i2 => aux567_a, i1 => auxsc6, i0 => auxsc10); auxsc2618 : nao2o22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2618, i3 => auxsc2630, i2 => auxreg4, i1 => auxsc2629, i0 => auxsc1626); auxsc2630 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2630, i2 => auxsc2623, i1 => auxsc2620, i0 => auxreg5); auxsc2623 : inv_x1 PORT MAP ( vss => vss, vdd =%3 E vdd, nq => auxsc2623, i => auxsc2622); auxsc2622 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2622, i1 => auxreg5, i0 => auxsc2621); auxsc2621 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2621, i1 => auxsc7, i0 => auxsc645); auxsc2620 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2620, i1 => auxsc27, i0 => aux591_a); auxsc2629 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2629, i1 => auxreg6, i0 => auxsc1028); auxsc2606 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq % 3D> auxsc2606, i2 => auxreg7, i1 => auxsc2561, i0 => auxsc2599); auxsc2561 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2561, i2 => auxsc1853, i1 => auxreg6, i0 => aux569_a); auxsc2599 : oa2a2a2a24_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2599, i7 => auxreg6, i6 => auxsc10, i5 => auxsc352, i4 => auxsc2563, i3 => aux736_a, i2 => auxsc2578, i1 => auxreg5, i0 => auxsc1886); auxsc2563 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2563, i2 => auxsc2594, i1 => auxreg3, i0 => aux567_a); auxsc2594 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2594, i1 => auxsc10, i0 => auxsc6); auxsc2578 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2578, i1 => auxreg3, i0 => scout); auxsc2602 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2602, i3 => auxsc2601, i2 => auxsc423, i1 => auxsc2600, i0 => auxreg4); auxsc2601 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2601, i2 => auxsc2596, i1 => auxsc2595, i0 => auxsc745); auxsc2596 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, n q => auxsc2596, i1 => auxsc2025, i0 => auxsc1322); auxsc2595 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2595, i2 => auxreg5, i1 => auxsc27, i0 => aux567_a); auxsc745 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc745, i1 => auxreg3, i0 => auxsc6); auxsc2600 : noa2a2a23_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2600, i5 => auxsc2524, i4 => auxsc2590, i3 => auxsc2580, i2 => auxsc352, i1 => auxsc27, i0 => aux578_a); auxsc2590 : nxr2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2590, i1 => auxreg3, i0 => auxsc10); auxsc2580 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2580, i2 => auxreg6, i1 => auxsc7, i0 => auxsc10); auxsc2549 : nao2o22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2549, i3 => auxsc2557, i2 => auxsc423, i1 => auxsc2556, i0 => auxsc2296); auxsc2557 : noa2a22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2557, i3 => auxsc2545, i2 => auxsc352, i1 => auxsc2550, i0 => auxreg5); auxsc2545 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2545, i2 => auxreg6, %0 A i1 => auxreg3, i0 => auxsc102); auxsc2550 : oa2a22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2550, i3 => auxreg6, i2 => auxsc1711, i1 => auxsc7, i0 => auxsc10); auxsc2556 : noa2a22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2556, i3 => auxreg6, i2 => auxsc337, i1 => auxsc7, i0 => auxsc102); auxsc337 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc337, i1 => auxreg2, i0 => auxsc10); auxsc2534 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2534, i2 => auxreg7, i1 => auxsc2533, i 0 => auxsc2532); auxsc2533 : a4_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2533, i3 => auxsc2515, i2 => auxsc2516, i1 => auxsc2517, i0 => auxsc2514); auxsc2515 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2515, i2 => auxsc1046, i1 => auxsc2492, i0 => aux646_a); auxsc2492 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2492, i1 => auxreg6, i0 => scout); auxsc2516 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2516, i1 => auxsc1952, i0 => auxsc2508); auxsc2508 : no2_x1 PORT MAP ( vss => v ss, vdd => vdd, nq => auxsc2508, i1 => aux569_a, i0 => scout); auxsc2517 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2517, i1 => auxsc2025, i0 => auxsc1322); auxsc2514 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2514, i1 => auxsc1028, i0 => auxsc1711); auxsc1711 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1711, i1 => auxreg3, i0 => aux567_a); auxsc2532 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2532, i1 => auxsc2512, i0 => auxreg4); auxsc2512 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2512, i2 => auxsc352, i1 => auxreg6, i0 => auxsc1901); auxsc2531 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2531, i1 => auxreg7, i0 => auxsc2530); auxsc2530 : oa2a22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2530, i3 => auxsc2529, i2 => auxsc2520, i1 => auxsc2524, i0 => auxsc2527); auxsc2529 : a3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2529, i2 => auxsc27, i1 => auxsc2528, i0 => auxreg4); auxsc2528 : nxr2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2528, i1 => auxreg5, i0 => auxsc10); auxsc2520 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2520, i3 => auxsc7, i2 => auxsc2511, i1 => auxreg3, i0 => auxreg2); auxsc2511 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2511, i1 => auxreg2, i0 => auxsc10); auxsc2524 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2524, i1 => auxreg6, i0 => auxsc352); auxsc2527 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2527, i1 => auxsc423, i0 => auxsc2526); auxsc2526 : nxr2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2526, i1 => auxsc2500, i0 => auxsc10); auxsc2500 : nxr2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2500, i1 => auxreg3, i0 => auxsc6); auxsc2472 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2472, i1 => auxsc27, i0 => auxsc2465); auxsc2465 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2465, i2 => auxsc2470, i1 => auxsc2468, i0 => auxsc2467); auxsc2470 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2470, i2 => auxsc2469, i1 => auxreg5, i0 => auxsc7); auxsc2469 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2469, i3 => auxreg3, i2 => auxreg2, i1 => auxsc6, i0 => auxsc10); auxsc2468 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2468, i1 => auxreg5, i0 => auxreg3); auxsc2467 : nxr2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2467, i1 => auxreg4, i0 => auxsc1612); auxsc2456 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2456, i2 => auxreg7, i1 => auxsc2342, i0 => auxsc2341); auxsc2455 : ao2o22_x2 PORT MAP ( vss => v ss, vdd => vdd, q => auxsc2455, i3 => auxsc2454, i2 => auxsc2453, i1 => auxsc2452, i0 => auxreg4); auxsc2454 : a3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2454, i2 => auxsc2449, i1 => auxsc2450, i0 => auxreg5); auxsc2449 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2449, i1 => auxreg6, i0 => auxsc1651); auxsc2450 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2450, i1 => auxreg6, i0 => auxsc2446); auxsc2446 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2446, i1 => auxreg3,%0 D i0 => auxsc213); auxsc2453 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2453, i1 => auxsc2448, i0 => auxreg4); auxsc2448 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2448, i1 => auxsc352, i0 => auxsc1322); auxsc2452 : no4_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2452, i3 => aux658_a, i2 => aux661_a, i1 => auxsc2429, i0 => auxsc2432); auxsc2429 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2429, i1 => auxreg5, i0 => auxsc2447); auxsc2447 : no2_x1 PORT MAP ( vss => vss, vdd % 3D> vdd, nq => auxsc2447, i1 => auxsc7, i0 => auxsc6); auxsc2432 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2432, i1 => auxreg3, i0 => aux587_a); auxsc2426 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2426, i2 => auxreg7, i1 => auxsc2425, i0 => auxsc2424); auxsc2425 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2425, i1 => auxsc2421, i0 => auxreg4); auxsc2421 : noa2a2a2a24_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2421, i7 => auxsc27, i6 => auxsc1651, i5 => aux600_a, i4 %3 D> auxsc352, i3 => auxreg6, i2 => auxsc2411, i1 => auxreg5, i0 => auxsc2337); auxsc2411 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2411, i1 => auxsc2373, i0 => auxreg2); auxsc2424 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2424, i2 => auxsc2418, i1 => auxsc2419, i0 => auxsc423); auxsc2418 : a4_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2418, i3 => auxsc2416, i2 => auxsc2415, i1 => auxsc352, i0 => auxsc2414); auxsc2416 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2416, i1 => auxreg6, i0 => auxsc7); auxsc2415 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2415, i1 => auxreg6, i0 => auxsc2409); auxsc2409 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2409, i1 => auxsc6, i0 => auxreg3); auxsc2414 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2414, i2 => auxsc1320, i1 => auxreg3, i0 => auxsc6); auxsc2419 : a4_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2419, i3 => auxsc728, i2 => auxsc2412, i1 => auxreg5, i0 => auxsc7); auxsc2412 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2412, i1 => auxreg6, i0 => auxsc1320); auxsc2387 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2387, i2 => auxsc423, i1 => auxsc2386, i0 => auxsc2385); auxsc2386 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2386, i1 => auxsc2380, i0 => auxsc2379); auxsc2380 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2380, i2 => auxsc7, i1 => auxreg6, i0 => auxsc102); auxsc2379 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2379, i1 => auxsc352, i0 %3 D> aux647_a); auxsc2385 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2385, i2 => auxsc352, i1 => auxsc728, i0 => auxsc2377); auxsc728 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc728, i1 => auxreg6, i0 => auxreg2); auxsc2377 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2377, i1 => auxreg6, i0 => auxsc2373); auxsc2373 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2373, i1 => auxsc7, i0 => auxsc10); auxsc2384 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2384, i2 => auxreg4, i1 => auxsc1791, i0 => auxsc2383); auxsc2383 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2383, i2 => auxsc1764, i1 => auxsc2356, i0 => auxsc2359); auxsc2356 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2356, i1 => auxreg5, i0 => auxsc14); auxsc2359 : xr2_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2359, i1 => auxsc2016, i0 => scout); auxsc2349 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2349, i1 => auxreg7, i0 => auxsc2348); auxsc2348 : oa2a22_x2 PORT MAP ( vss % 3D> vss, vdd => vdd, q => auxsc2348, i3 => auxsc2347, i2 => auxsc2346, i1 => auxsc2345, i0 => auxsc2344); auxsc2347 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2347, i2 => auxsc2335, i1 => auxsc2334, i0 => auxsc2333); auxsc2335 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2335, i1 => auxsc2323, i0 => auxsc352); auxsc2323 : xr2_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2323, i1 => auxreg6, i0 => auxreg2); auxsc2334 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2334, i2 =% 3E auxreg6, i1 => auxsc7, i0 => auxsc10); auxsc2333 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2333, i1 => auxsc352, i0 => aux648_a); auxsc2346 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2346, i2 => auxreg4, i1 => auxsc7, i0 => auxsc102); auxsc2345 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2345, i1 => aux659_a, i0 => aux658_a); auxsc2344 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2344, i2 => auxreg4, i1 => auxsc2337, i0 => auxsc2336); auxsc2337 : no2_x1 PORT MAP ( % 0A vss => vss, vdd => vdd, nq => auxsc2337, i1 => auxsc7, i0 => scout); auxsc2336 : xr2_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2336, i1 => auxsc10, i0 => auxreg2); auxsc2343 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2343, i2 => auxreg7, i1 => auxsc2342, i0 => auxsc2341); auxsc2342 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2342, i2 => auxreg4, i1 => auxsc2025, i0 => auxsc2169); auxsc2341 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2341, i2 => auxreg4, i1 =% 3E auxsc2310, i0 => auxreg5); auxsc2310 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2310, i1 => auxreg6, i0 => auxsc348); auxsc2299 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2299, i3 => auxsc2298, i2 => auxsc423, i1 => auxsc2297, i0 => auxsc2296); auxsc2298 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2298, i3 => auxsc2292, i2 => auxsc2288, i1 => auxsc2271, i0 => auxsc6); auxsc2292 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2292, i => auxsc1925); auxsc2288 : inv_x1 P ORT MAP ( vss => vss, vdd => vdd, nq => auxsc2288, i => auxsc1902); auxsc2271 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2271, i1 => auxsc2270, i0 => aux615_a); auxsc2270 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2270, i1 => auxreg6, i0 => auxsc352); auxsc2297 : noa2a22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2297, i3 => auxreg6, i2 => aux570_a, i1 => auxreg3, i0 => aux582_a); auxsc2296 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2296, i1 => auxsc352, i0 => auxreg4) ; auxsc2291 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2291, i3 => auxsc2287, i2 => auxsc1270, i1 => auxsc2286, i0 => auxsc2072); auxsc2287 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2287, i1 => auxreg6, i0 => auxsc739); auxsc739 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc739, i1 => aux567_a, i0 => auxreg3); auxsc1270 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1270, i1 => auxsc352, i0 => auxsc423); auxsc2286 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2286, i1 => auxreg6, i0 => aux729_a); auxsc2267 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2267, i2 => auxsc2264, i1 => auxsc2257, i0 => auxsc2254); auxsc2264 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2264, i1 => auxreg7, i0 => auxsc2263); auxsc2263 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2263, i2 => auxsc2262, i1 => auxreg5, i0 => auxsc2258); auxsc2262 : oa2a22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2262, i3 => auxsc2261, i2 => auxsc2260, i1 => auxsc2259, i0 % 3D> auxreg4); auxsc2261 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2261, i1 => aux631_a, i0 => auxsc1046); auxsc2260 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2260, i1 => auxreg6, i0 => auxsc1651); auxsc1651 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1651, i1 => auxreg3, i0 => auxsc102); auxsc2259 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2259, i1 => aux611_a, i0 => aux649_a); auxsc2258 : a3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2258, i2 => auxsc423, %0 A i1 => auxsc2072, i0 => auxsc1901); auxsc2257 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2257, i2 => auxsc423, i1 => auxsc2256, i0 => auxsc2255); auxsc2256 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2256, i1 => auxsc2244, i0 => auxreg5); auxsc2244 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2244, i2 => aux605_a, i1 => auxreg6, i0 => auxsc2210); auxsc2210 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2210, i1 => scout, i0 => auxsc7); auxsc2255 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2255, i1 => auxsc2248, i0 => auxsc2246); auxsc2248 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2248, i1 => auxreg6, i0 => auxsc2247); auxsc2247 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2247, i2 => auxsc2238, i1 => auxreg3, i0 => scout); auxsc2238 : xr2_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2238, i1 => auxreg2, i0 => auxsc10); auxsc2246 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2246, i2 => auxsc352, i1 => auxreg3, i0 => auxsc10 2); auxsc2254 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2254, i1 => auxsc2253, i0 => auxsc1732); auxsc2253 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2253, i1 => auxreg6, i0 => auxsc106); auxsc2266 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2266, i1 => auxsc1261, i0 => auxsc2265); auxsc1261 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1261, i1 => auxreg7, i0 => auxsc423); auxsc2265 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2265, i2 => auxsc1916, i1 => auxsc2243, i0 => auxsc2242); auxsc2243 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2243, i1 => auxreg6, i0 => aux569_a); auxsc2242 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2242, i1 => auxreg5, i0 => auxsc2241); auxsc2241 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2241, i2 => auxsc2237, i1 => auxreg3, i0 => auxsc6); auxsc2237 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2237, i1 => auxsc6, i0 => auxsc10); auxsc2207 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2207, i2 => auxsc2206, i1 => auxreg7, i0 => auxsc2200); auxsc2206 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2206, i3 => auxsc1830, i2 => auxreg4, i1 => auxsc2201, i0 => auxsc1028); auxsc2201 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2201, i1 => auxreg6, i0 => aux568_a); auxsc2200 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2200, i2 => auxreg6, i1 => auxsc352, i0 => auxsc2144); auxsc2204 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2204, i1 => auxreg7,%0 D i0 => auxsc2203); auxsc2203 : noa2a22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2203, i3 => auxreg6, i2 => scout, i1 => aux737_a, i0 => aux568_a); auxsc2167 : o4_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2167, i3 => auxsc2185, i2 => auxsc2182, i1 => auxsc2180, i0 => auxsc2177); auxsc2185 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2185, i2 => auxreg7, i1 => auxsc2184, i0 => auxsc2183); auxsc2184 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2184, i2 => auxreg4, i1 => auxsc21 60, i0 => auxsc2162); auxsc2160 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2160, i2 => auxreg6, i1 => auxreg5, i0 => auxsc213); auxsc2162 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2162, i2 => auxreg6, i1 => auxsc352, i0 => auxsc2168); auxsc2168 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2168, i1 => auxreg3, i0 => auxsc10); auxsc2183 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2183, i1 => auxsc1046, i0 => auxsc1224); auxsc2182 : an12_x1 PORT MAP ( vss => vss, v dd => vdd, q => auxsc2182, i1 => auxreg7, i0 => auxsc2181); auxsc2181 : noa2a22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2181, i3 => aux738_a, i2 => auxsc2152, i1 => auxsc1975, i0 => auxsc2137); auxsc2152 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2152, i2 => auxsc2169, i1 => auxsc7, i0 => scout); auxsc2169 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2169, i1 => auxreg3, i0 => aux582_a); auxsc2180 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2180, i2 => auxsc423, i1 => auxsc2179, i0 => auxsc2178); auxsc2179 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2179, i1 => auxreg6, i0 => aux583_a); auxsc2178 : na3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2178, i2 => auxreg6, i1 => auxsc352, i0 => aux573_a); auxsc2177 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2177, i1 => auxreg6, i0 => auxsc2176); auxsc2176 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2176, i2 => aux729_a, i1 => auxreg3, i0 => auxreg2); auxsc2142 : nao2o22_x1 PORT MAP ( vss =% 3E vss, vdd => vdd, nq => auxsc2142, i3 => auxsc1028, i2 => auxsc2144, i1 => auxreg5, i0 => auxsc2143); auxsc2144 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2144, i1 => auxreg3, i0 => auxsc956); auxsc2143 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2143, i1 => auxsc423, i0 => aux568_a); auxsc2136 : oa2a22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2136, i3 => auxsc1975, i2 => aux622_a, i1 => aux738_a, i0 => auxsc2137); auxsc2137 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2 137, i1 => auxsc7, i0 => aux582_a); auxsc2133 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2133, i2 => auxsc2131, i1 => auxsc1940, i0 => auxsc1939); auxsc2131 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2131, i => auxsc2130); auxsc2130 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2130, i1 => auxreg7, i0 => auxsc2129); auxsc2129 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2129, i3 => auxreg5, i2 => auxsc2128, i1 => auxsc423, i0 => auxsc2123); auxsc2128 : o2_x2 PORT MAP (% 0D vss => vss, vdd => vdd, q => auxsc2128, i1 => auxreg4, i0 => auxsc1901); auxsc2123 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2123, i1 => auxsc7, i0 => auxsc213); auxsc2132 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2132, i1 => auxreg6, i0 => auxsc10); auxsc2103 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2103, i2 => auxsc2112, i1 => auxsc1940, i0 => auxsc1939); auxsc2112 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2112, i => auxsc2111); auxsc2111 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2111, i1 => auxreg7, i0 => auxsc2110); auxsc2110 : noa2a22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2110, i3 => aux736_a, i2 => auxsc2109, i1 => auxsc352, i0 => auxsc2108); auxsc2109 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2109, i1 => auxreg3, i0 => aux567_a); auxsc2108 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2108, i1 => auxsc423, i0 => aux588_a); auxsc2089 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2089, i2 => auxreg7%2 C i1 => auxsc2094, i0 => auxsc2092); auxsc2094 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2094, i1 => auxsc2093, i0 => auxsc1853); auxsc2093 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2093, i2 => auxsc1939, i1 => auxsc27, i0 => auxsc425); auxsc425 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc425, i1 => auxsc8, i0 => auxreg3); auxsc2092 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2092, i1 => auxsc1852, i0 => auxsc1028); auxsc1028 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1028, i1 => auxreg5, i0 => auxreg4); auxsc2085 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2085, i1 => auxreg7, i0 => auxsc2095); auxsc2095 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2095, i1 => auxreg4, i0 => auxsc2091); auxsc2091 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2091, i1 => auxsc213, i0 => auxsc7); auxsc2065 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2065, i2 => auxsc2081, i1 => auxsc2079, i0 => auxsc2077); auxsc2081 : nao2o22_x1 PORT MA P ( vss => vss, vdd => vdd, nq => auxsc2081, i3 => auxreg7, i2 => auxsc2075, i1 => auxsc2080, i0 => auxsc1957); auxsc2075 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2075, i3 => auxsc1732, i2 => auxsc2072, i1 => auxsc2071, i0 => auxsc2070); auxsc2072 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2072, i1 => auxsc7, i0 => aux582_a); auxsc2070 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2070, i3 => auxreg3, i2 => scout, i1 => auxreg2, i0 => auxsc10); auxsc2080 : o2_x2 PORT MA P ( vss => vss, vdd => vdd, q => auxsc2080, i1 => auxsc27, i0 => auxsc1732); auxsc2079 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2079, i1 => auxreg7, i0 => auxsc2078); auxsc2078 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2078, i2 => auxsc2073, i1 => auxsc2067, i0 => auxreg4); auxsc2073 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2073, i2 => auxsc2068, i1 => auxsc423, i0 => auxsc392); auxsc2068 : xr2_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2068, i1 => auxreg5, i0 => auxsc7); auxsc2067 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2067, i2 => auxsc1915, i1 => auxsc352, i0 => aux588_a); auxsc2077 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2077, i2 => auxsc27, i1 => auxsc2071, i0 => auxsc2076); auxsc2071 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2071, i1 => auxreg5, i0 => auxsc423); auxsc2076 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2076, i1 => auxsc1628, i0 => auxsc2015); auxsc2011 : o3_x2 PORT MAP ( vss => vss, vdd => v dd, q => auxsc2011, i2 => auxsc2044, i1 => auxsc2042, i0 => auxsc2037); auxsc2044 : nao2o22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2044, i3 => auxreg7, i2 => auxsc2029, i1 => auxsc2043, i0 => auxsc423); auxsc2029 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2029, i3 => auxsc2021, i2 => auxsc423, i1 => auxsc1732, i0 => auxsc2020); auxsc2021 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2021, i2 => auxsc2017, i1 => auxreg5, i0 => aux597_a); auxsc2017 : na3_x1 PORT MAP ( vss => vss, v dd => vdd, nq => auxsc2017, i2 => auxreg5, i1 => aux627_a, i0 => scout); auxsc1732 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1732, i1 => auxreg5, i0 => auxsc423); auxsc2020 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2020, i3 => auxreg3, i2 => auxreg2, i1 => auxreg2, i0 => auxsc10); auxsc2043 : noa2a22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2043, i3 => auxsc1981, i2 => auxsc2034, i1 => aux732_a, i0 => auxsc1255); auxsc1981 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q =%3 E auxsc1981, i2 => auxreg6, i1 => auxsc2016, i0 => auxsc1612); auxsc2016 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2016, i1 => auxsc6, i0 => auxreg3); auxsc2034 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2034, i1 => auxsc352, i0 => auxsc1982); auxsc1982 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1982, i1 => auxsc2015, i0 => auxsc1628); auxsc2015 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2015, i2 => auxreg3, i1 => auxreg2, i0 => scout); auxsc1255 : na2_x1 PORT MAP (%0 D vss => vss, vdd => vdd, nq => auxsc1255, i1 => auxreg3, i0 => aux578_a); auxsc2042 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2042, i1 => auxreg7, i0 => auxsc2041); auxsc2041 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2041, i2 => auxsc2040, i1 => auxsc2038, i0 => auxsc423); auxsc2040 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2040, i2 => auxsc2039, i1 => auxsc1999, i0 => auxsc352); auxsc2039 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2039, i2 => auxreg4, i1 => auxsc7, i0 => aux587_a); auxsc1999 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1999, i2 => auxsc2014, i1 => auxreg6, i0 => scout); auxsc2014 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2014, i2 => auxreg6, i1 => auxreg3, i0 => auxreg2); auxsc2038 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2038, i1 => auxreg5, i0 => auxsc1865); auxsc2037 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2037, i1 => auxsc2036, i0 => auxreg4); auxsc2036 : ao2o22_x2 PORT MAP ( vss =%3 E vss, vdd => vdd, q => auxsc2036, i3 => auxsc2025, i2 => auxsc2024, i1 => auxsc2023, i0 => auxsc352); auxsc2025 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2025, i1 => auxreg6, i0 => auxreg5); auxsc2024 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc2024, i3 => aux569_a, i2 => auxsc10, i1 => auxsc7, i0 => auxsc6); auxsc2023 : noa2a22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc2023, i3 => auxreg6, i2 => auxsc106, i1 => auxsc7, i0 => aux590_a); auxsc1973 : oa2a22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1973, i3 => auxsc1975, i2 => aux601_a, i1 => aux736_a, i0 => auxsc1974); auxsc1975 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1975, i1 => auxreg5, i0 => auxsc423); auxsc1974 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1974, i1 => auxsc7, i0 => aux590_a); auxsc1970 : a3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1970, i2 => aux733_a, i1 => auxreg5, i0 => auxreg4); auxsc1969 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1969, i1 => auxreg3, i0 => auxsc1911); auxsc1967 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1967, i1 => auxsc1951, i0 => auxsc423); auxsc754 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc754, i1 => auxsc645, i0 => auxsc7); auxsc645 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc645, i1 => scout, i0 => auxsc6); auxsc1962 : na3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1962, i2 => aux733_a, i1 => auxreg5, i0 => auxreg4); auxsc1961 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1961, i1 => auxreg3, i0 => auxsc213); auxsc1951 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1951, i1 => auxreg7, i0 => auxsc128); auxsc1952 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1952, i1 => auxreg6, i0 => auxsc352); auxsc1956 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1956, i1 => auxreg4, i0 => auxsc1957); auxsc1957 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1957, i2 => auxreg3, i1 => auxreg2, i0 => scout); auxsc1948 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1948, i => auxsc1947); auxsc1947 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1947, i1 => auxreg7, i0 => auxsc1946); auxsc1946 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1946, i2 => auxsc1945, i1 => auxreg6, i0 => auxsc1941); auxsc1945 : on12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1945, i1 => auxreg6, i0 => auxsc1944); auxsc1944 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1944, i => auxsc1943); auxsc1943 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q =% 3E auxsc1943, i1 => auxreg5, i0 => auxsc1942); auxsc1942 : noa2a22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1942, i3 => auxreg3, i2 => auxsc10, i1 => auxsc6, i0 => scout); auxsc1941 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1941, i1 => auxreg4, i0 => aux613_a); auxsc1940 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1940, i1 => auxsc1805, i0 => auxreg5); auxsc1939 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1939, i1 => auxreg6, i0 => auxsc348); auxsc348 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc348, i1 => aux582_a, i0 => auxsc7); auxsc1900 : a3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1900, i2 => auxreg7, i1 => auxsc1918, i0 => auxsc1913); auxsc1918 : na3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1918, i2 => auxsc1917, i1 => auxsc1916, i0 => auxsc423); auxsc1917 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1917, i1 => auxsc1906, i0 => auxreg5); auxsc1906 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1906, i2 => aux609_a, i1 => auxsc1891, i0 => auxreg2); auxsc1891 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1891, i1 => auxreg6, i0 => auxreg3); auxsc1916 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1916, i => auxsc1915); auxsc1915 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1915, i1 => auxreg5, i0 => auxsc1914); auxsc1914 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1914, i1 => auxreg3, i0 => aux578_a); auxsc1913 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1913, i1 => aux770_a, i0 => auxsc1897); auxsc1897 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1897, i1 => auxreg5, i0 => auxsc1901); auxsc1876 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1876, i2 => auxreg7, i1 => auxsc1923, i0 => auxsc1922); auxsc1923 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1923, i2 => auxsc423, i1 => auxreg6, i0 => auxsc1901); auxsc1922 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1922, i2 => aux611_a, i1 => auxsc1874, i0 => auxsc423); auxsc1874 : a2_x2 PORT MAP ( vss => v ss, vdd => vdd, q => auxsc1874, i1 => auxreg5, i0 => auxsc1006); auxsc1926 : oa2a2a23_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1926, i5 => auxsc1921, i4 => auxreg4, i3 => auxsc1888, i2 => auxsc423, i1 => auxsc1925, i0 => auxsc1924); auxsc1921 : nao2o22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1921, i3 => auxsc1920, i2 => auxsc1919, i1 => auxsc27, i0 => auxsc1911); auxsc1920 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1920, i1 => auxreg6, i0 => auxsc1612); auxsc1919 : na2_x1 PORT MAP ( v ss => vss, vdd => vdd, nq => auxsc1919, i1 => auxsc352, i0 => auxsc1880); auxsc1880 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1880, i1 => aux566_a, i0 => aux569_a); auxsc1911 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1911, i => auxsc1232); auxsc1888 : oa2a22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1888, i3 => aux731_a, i2 => auxsc1886, i1 => auxsc1908, i0 => auxreg5); auxsc1886 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1886, i1 => auxsc1006, i0 => auxsc1902); auxsc1 006 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1006, i1 => auxsc213, i0 => auxreg3); auxsc1902 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1902, i1 => auxreg3, i0 => aux578_a); auxsc1908 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1908, i1 => auxreg6, i0 => auxsc6); auxsc1925 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1925, i1 => auxreg6, i0 => auxsc352); auxsc1924 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1924, i2 => auxreg3, i1 => auxreg2, i 0 => auxsc10); auxsc1858 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1858, i2 => auxreg7, i1 => auxsc1857, i0 => auxsc1856); auxsc1857 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1857, i2 => auxsc423, i1 => auxsc1848, i0 => auxsc1849); auxsc1848 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1848, i2 => auxreg6, i1 => auxreg5, i0 => auxsc106); auxsc1849 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1849, i1 => auxreg6, i0 => auxsc1846); auxsc1846 : na2_x1 PORT MAP ( vss => vs s, vdd => vdd, nq => auxsc1846, i1 => auxreg3, i0 => auxsc1232); auxsc1856 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1856, i2 => auxsc1853, i1 => auxsc1851, i0 => auxsc1852); auxsc1853 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1853, i1 => auxsc352, i0 => auxsc423); auxsc1851 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1851, i1 => auxreg6, i0 => auxsc1628); auxsc1852 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1852, i1 => auxreg6, i0 => auxsc343); auxsc1831 : ao2o22 _x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1831, i3 => auxsc1830, i2 => auxreg4, i1 => auxsc1829, i0 => auxsc423); auxsc1830 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1830, i1 => aux592_a, i0 => auxsc352); auxsc1829 : noa2a22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1829, i3 => aux731_a, i2 => auxsc1704, i1 => auxsc27, i0 => auxsc1827); auxsc1704 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1704, i1 => auxreg3, i0 => aux578_a); auxsc1827 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1827, i1 => auxreg5, i0 => aux588_a); auxsc1832 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1832, i1 => auxreg6, i0 => aux595_a); auxsc1806 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1806, i1 => auxsc1805, i0 => auxreg5); auxsc1805 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1805, i1 => auxreg7, i0 => auxreg4); auxsc1804 : oa2a22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1804, i3 => auxsc27, i2 => aux569_a, i1 => auxreg6, i0 => auxsc1801); auxsc1801 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1801, i2 => auxreg3, i1 => auxsc6, i0 => auxsc10); auxsc1809 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1809, i1 => auxsc423, i0 => auxreg7); auxsc1808 : oa2a22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1808, i3 => auxsc1791, i2 => auxsc1807, i1 => auxreg6, i0 => aux583_a); auxsc1791 : xr2_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1791, i1 => auxreg6, i0 => auxreg3); auxsc1807 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q % 3D> auxsc1807, i1 => auxsc352, i0 => aux567_a); auxsc1784 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1784, i3 => auxreg6, i2 => auxsc1783, i1 => auxsc1782, i0 => auxsc423); auxsc1783 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1783, i1 => aux729_a, i0 => aux579_a); auxsc1782 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1782, i1 => auxsc352, i0 => aux576_a); auxsc1785 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1785, i1 => auxreg6, i0 => aux580_a); auxsc1773 : an12_x1 P ORT MAP ( vss => vss, vdd => vdd, q => auxsc1773, i1 => auxreg7, i0 => auxsc27); auxsc1772 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1772, i1 => auxsc1761, i0 => auxsc1757); auxsc1761 : o4_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1761, i3 => auxsc1768, i2 => auxsc1767, i1 => auxsc1765, i0 => auxreg4); auxsc1768 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1768, i1 => auxsc27, i0 => auxsc1759); auxsc1759 : oa2a22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1759, i3 => auxsc7,%0 D i2 => auxsc6, i1 => auxreg3, i0 => aux567_a); auxsc1767 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1767, i2 => auxsc27, i1 => auxreg5, i0 => auxsc1766); auxsc1766 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1766, i1 => auxsc7, i0 => aux567_a); auxsc1765 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1765, i2 => auxsc1709, i1 => auxsc352, i0 => auxreg6); auxsc1709 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1709, i1 => auxreg2, i0 => auxreg3); auxsc1757 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1757, i2 => auxreg4, i1 => auxreg6, i0 => auxsc1769); auxsc1769 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1769, i1 => auxsc1764, i0 => auxsc1478); auxsc1764 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1764, i1 => auxreg5, i0 => auxreg2); auxsc1478 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1478, i1 => auxreg3, i0 => scout); auxsc1647 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1647, i1 => auxsc1644, i0 => frz); auxsc1644 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1644, i3 => auxsc1631, i2 => auxreg7, i1 => auxsc352, i0 => auxsc1630); auxsc1631 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1631, i3 => auxsc1046, i2 => auxsc1609, i1 => auxsc1607, i0 => auxsc1605); auxsc1046 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1046, i1 => auxreg5, i0 => auxreg4); auxsc1609 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1609, i1 => auxsc1608, i0 => auxreg6); auxsc1608 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1608, i3 => auxsc1602, i2 => auxsc1601, i1 => auxsc343, i0 => auxsc1600); auxsc1602 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1602, i2 => auxsc1224, i1 => auxsc313, i0 => ir_opcod(16)); auxsc1224 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1224, i1 => auxreg3, i0 => aux582_a); auxsc313 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc313, i1 => ir_opcod(18), i0 => ir_opcod(17)); auxsc1601 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1601,%0 D i1 => auxsc1573, i0 => auxsc40); auxsc1573 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1573, i1 => auxsc1570, i0 => ir_opcod(15)); auxsc1570 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1570, i2 => auxsc1568, i1 => auxsc848, i0 => ir_opcod(13)); auxsc1568 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1568, i1 => auxsc1567, i0 => ir_opcod(5)); auxsc1567 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1567, i2 => ir_opcod(2), i1 => auxsc278, i0 => ir_opcod(1)); auxsc343 : o2_ x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc343, i1 => auxreg3, i0 => auxreg2); auxsc1600 : na3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1600, i2 => scout, i1 => auxsc1552, i0 => auxsc50); auxsc1552 : oa2a2a23_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1552, i5 => auxsc1550, i4 => auxsc37, i3 => auxsc1556, i2 => ir_opcod(18), i1 => auxsc1555, i0 => aux699_a); auxsc1607 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1607, i2 => auxsc7, i1 => auxreg2, i0 => auxsc1606); auxsc1606 : o2 _x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1606, i1 => scout, i0 => auxsc1332); auxsc1332 : na4_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1332, i3 => auxsc690, i2 => auxsc21, i1 => auxsc50, i0 => ir_opcod(16)); auxsc690 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc690, i1 => aux687_a, i0 => auxsc39); auxsc1605 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1605, i1 => aux736_a, i0 => auxsc27); auxsc1630 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1630, i1 =% 3E auxsc1621, i0 => auxsc1629); auxsc1621 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1621, i1 => auxsc171, i0 => auxreg4); auxsc1629 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1629, i2 => auxsc1628, i1 => auxsc1627, i0 => auxsc1612); auxsc1628 : on12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1628, i1 => auxreg3, i0 => auxsc392); auxsc392 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc392, i1 => auxsc6, i0 => auxsc10); auxsc1627 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1627, i1 => auxsc1626, i0 => auxsc1625); auxsc1626 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1626, i1 => auxreg3, i0 => auxsc213); auxsc213 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc213, i1 => auxreg2, i0 => scout); auxsc1625 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1625, i => auxsc1624); auxsc1624 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1624, i1 => auxreg2, i0 => auxsc1623); auxsc1623 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1623,%0 D i2 => auxsc10, i1 => auxsc1622, i0 => ir_opcod(17)); auxsc1622 : noa2a2a23_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1622, i5 => auxsc1550, i4 => auxsc37, i3 => auxsc1556, i2 => ir_opcod(18), i1 => aux699_a, i0 => auxsc1555); auxsc1550 : nao2o22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1550, i3 => auxsc1554, i2 => auxsc21, i1 => auxsc105, i0 => ir_opcod(18)); auxsc1554 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1554, i3 => auxsc20, i2 => ir_opcod(15), i1 => auxsc39, i0 => ir_opcod(14) ); auxsc1556 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1556, i1 => auxsc39, i0 => auxsc40); auxsc1555 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1555, i1 => auxsc21, i0 => ir_opcod(16)); auxsc1612 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1612, i1 => auxsc6, i0 => auxsc10); auxsc1646 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1646, i2 => auxsc1641, i1 => auxsc1643, i0 => auxsc1638); auxsc1641 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1641, i2 %3 D> auxsc1640, i1 => auxreg3, i0 => auxsc1639); auxsc1640 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1640, i1 => aux729_a, i0 => auxreg6); auxsc1639 : na3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1639, i2 => aux587_a, i1 => aux720_a, i0 => auxsc50); auxsc1643 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1643, i2 => auxsc1642, i1 => auxsc128, i0 => auxsc27); auxsc1642 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1642, i1 => auxsc1632, i0 => aux569_a); auxsc1632 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1632, i1 => auxreg5, i0 => auxsc1541); auxsc1541 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1541, i1 => auxreg4, i0 => auxsc171); auxsc128 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc128, i => frz); auxsc1638 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1638, i2 => auxsc1637, i1 => auxsc10, i0 => auxsc1636); auxsc1637 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1637, i1 => auxsc455, i0 => auxsc454); auxsc455 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc455, i => reset); auxsc454 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc454, i => test); auxsc1636 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1636, i1 => auxsc171, i0 => auxsc27); auxsc171 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc171, i => auxreg7); auxsc1232 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1232, i1 => auxreg2, i0 => scout); auxsc27 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc27, i % 3D> auxreg6); auxsc102 : xr2_x1 PORT MAP ( vss => vss, vdd => vdd, q => auxsc102, i1 => auxreg2, i0 => scout); auxsc1322 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1322, i1 => auxreg3, i0 => auxsc1320); auxsc1320 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1320, i1 => auxsc6, i0 => auxsc10); auxsc106 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc106, i1 => auxreg3, i0 => auxreg2); auxsc956 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc956, i1 => auxreg2, i0 =%3 E auxsc10); auxsc9 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc9, i1 => auxsc8, i0 => auxreg3); auxsc8 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc8, i1 => auxsc6, i0 => scout); auxsc6 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc6, i => auxreg2); auxsc10 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc10, i => scout); auxsc7 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc7, i => auxreg3); auxsc703 : an12_x1 PORT MAP ( vss => vss, vdd => vdd, % 0A q => auxsc703, i1 => scout, i0 => auxreg3); auxsc14 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc14, i1 => auxreg2, i0 => scout); auxsc543 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc543, i1 => aux757_a, i0 => ir_opcod(18)); auxsc472 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc472, i1 => auxsc471, i0 => ir_opcod(8)); auxsc471 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc471, i => ir_opcod(10)); auxsc879 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => au xsc879, i2 => ir_opcod(17), i1 => auxsc878, i0 => auxsc877); auxsc878 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc878, i2 => ir_opcod(16), i1 => auxsc874, i0 => auxsc875); auxsc874 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc874, i2 => ir_opcod(14), i1 => auxsc865, i0 => auxsc866); auxsc865 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc865, i2 => auxsc847, i1 => auxsc845, i0 => ir_opcod(18)); auxsc847 : no4_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc847, i3 => auxsc846%2 C i2 => aux712_a, i1 => ir_opcod(13), i0 => ir_opcod(5)); auxsc846 : na3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc846, i2 => auxsc47, i1 => auxsc46, i0 => ir_opcod(4)); auxsc845 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc845, i1 => auxsc830, i0 => auxsc20); auxsc830 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc830, i1 => ir_opcod(7), i0 => ir_opcod(6)); auxsc866 : o3_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc866, i2 => auxsc848, i1 => auxsc515, i0 => ir_opcod(13))%3 B auxsc848 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc848, i1 => auxsc482, i0 => auxsc63); auxsc482 : nao22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc482, i2 => ir_opcod(3), i1 => auxsc45, i0 => ir_opcod(2)); auxsc875 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc875, i1 => auxsc864, i0 => auxsc860); auxsc864 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc864, i2 => auxsc863, i1 => auxsc862, i0 => auxsc861); auxsc863 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q =% 3E auxsc863, i1 => auxsc857, i0 => auxsc856); auxsc857 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc857, i1 => auxsc47, i0 => ir_opcod(1)); auxsc47 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc47, i => ir_opcod(3)); auxsc856 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc856, i2 => ir_opcod(3), i1 => auxsc45, i0 => ir_opcod(0)); auxsc45 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc45, i => ir_opcod(1)); auxsc862 : na4_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc862, i3 => auxsc40, i2 => auxsc20, i1 => auxsc515, i0 => auxsc63); auxsc515 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc515, i => ir_opcod(5)); auxsc861 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc861, i2 => auxsc46, i1 => auxsc278, i0 => ir_opcod(1)); auxsc46 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc46, i => ir_opcod(2)); auxsc860 : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc860, i1 => auxsc859, i0 => ir_opcod(18)); auxsc859 : na2_x1 PORT MAP ( vss = > vss, vdd => vdd, nq => auxsc859, i1 => auxsc105, i0 => ir_opcod(15)); auxsc877 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc877, i2 => auxsc37, i1 => auxsc872, i0 => auxsc871); auxsc872 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc872, i2 => ir_opcod(18), i1 => auxsc105, i0 => ir_opcod(15)); auxsc871 : oa22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc871, i2 => ir_opcod(15), i1 => auxsc20, i0 => ir_opcod(14)); auxsc20 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc20% 2C i => ir_opcod(13)); auxsc295 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc295, i2 => auxsc23, i1 => auxsc92, i0 => auxsc50); auxsc1319 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1319, i3 => auxsc1317, i2 => auxsc92, i1 => auxsc1119, i0 => auxsc37); auxsc1317 : ao22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1317, i2 => auxsc74, i1 => auxsc1315, i0 => auxsc1116); auxsc74 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc74, i1 => auxsc40, i0 => ir_opcod(13)); auxsc1315 : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1315, i2 => ir_opcod(13), i1 => auxsc1310, i0 => auxsc1309); auxsc1310 : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1310, i2 => auxsc500, i1 => auxsc63, i0 => ir_opcod(5)); auxsc500 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc500, i1 => ir_opcod(3), i0 => ir_opcod(2)); auxsc63 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc63, i => ir_opcod(4)); auxsc1309 : nxr2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1309, i1 => auxsc278, i0 => ir_opcod(1)); auxsc278 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc278, i => ir_opcod(0)); auxsc1116 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1116, i1 => auxsc39, i0 => auxsc40); auxsc39 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc39, i => ir_opcod(15)); auxsc40 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc40, i => ir_opcod(14)); auxsc1119 : ao2o22_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1119, i3 => auxsc1078, i2 => auxsc105, i1 => ir_opcod(18), i0 => ir_opcod(15)); auxsc1078 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1078, i1 => ir_opcod(18), i0 => ir_opcod(15)); auxsc105 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc105, i1 => ir_opcod(14), i0 => ir_opcod(13)); auxsc1318 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1318, i1 => auxsc23, i0 => auxsc92); auxsc23 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc23, i1 => auxsc24, i0 => ir_opcod(13)); auxsc24 : o2_x2 PORT MAP ( vss => vss, vdd %3 D> vdd, q => auxsc24, i1 => ir_opcod(15), i0 => ir_opcod(14)); auxsc92 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc92, i1 => auxsc21, i0 => auxsc37); auxsc21 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc21, i => ir_opcod(18)); auxsc37 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc37, i => ir_opcod(16)); auxsc50 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc50, i => ir_opcod(17)); auxsc423 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc423, i => aux reg4); auxsc1865 : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => auxsc1865, i1 => aux568_a, i0 => aux603_a); auxsc352 : inv_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc352, i => auxreg5); auxsc1901 : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => auxsc1901, i1 => auxreg3, i0 => aux590_a); aux775_a : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => aux775_a, i2 => auxsc352, i1 => auxreg6, i0 => auxsc1901); aux770_a : noa22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => aux770_a, i2 => auxsc423, i1 =% 3E auxreg5, i0 => auxsc1865); aux723_a : nao2o22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => aux723_a, i3 => auxsc1319, i2 => ir_opcod(17), i1 => auxsc1318, i0 => auxsc50); aux720_a : a3_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux720_a, i2 => aux699_a, i1 => auxsc21, i0 => ir_opcod(16)); aux718_a : no3_x1 PORT MAP ( vss => vss, vdd => vdd, nq => aux718_a, i2 => ir_opcod(3), i1 => ir_opcod(1), i0 => ir_opcod(0)); aux713_a : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux713_a, i1 => auxsc879, i0 => auxsc295); aux712_a : xr2_x1 PORT MAP ( vss => vss, vdd => vdd, q => aux712_a, i1 => ir_opcod(1), i0 => ir_opcod(0)); aux706_a : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => aux706_a, i1 => scout, i0 => auxsc472); aux699_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux699_a, i1 => auxsc105, i0 => ir_opcod(15)); aux696_a : a3_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux696_a, i2 => auxsc543, i1 => aux677_a, i0 => auxsc39); aux687_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux687_a, %0 A i1 => ir_opcod(14), i0 => ir_opcod(13)); aux685_a : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => aux685_a, i1 => resnul, i0 => alu_sign); aux681_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux681_a, i1 => auxsc45, i0 => ir_opcod(3)); aux677_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux677_a, i1 => auxsc40, i0 => ir_opcod(13)); aux676_a : a3_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux676_a, i2 => auxsc39, i1 => auxsc40, i0 => ir_opcod(18)); aux672_a : a2_x2 PORT MAP ( vss => vss,%0 D vdd => vdd, q => aux672_a, i1 => aux762_a, i0 => auxsc20); aux671_a : xr2_x1 PORT MAP ( vss => vss, vdd => vdd, q => aux671_a, i1 => auxsc14, i0 => auxreg3); aux661_a : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => aux661_a, i1 => auxreg6, i0 => aux601_a); aux659_a : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => aux659_a, i1 => auxreg6, i0 => auxreg3); aux658_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux658_a, i1 => auxsc352, i0 => auxreg6); aux649_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux649_a, i1 => auxreg5, i0 => auxsc703); aux648_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux648_a, i1 => scout, i0 => auxsc7); aux647_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux647_a, i1 => auxsc7, i0 => auxreg2); aux646_a : na2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => aux646_a, i1 => auxreg6, i0 => aux569_a); aux633_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux633_a, i1 => auxsc10, i0 => auxreg6); aux631_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd%2 C q => aux631_a, i1 => auxsc9, i0 => auxreg6); aux627_a : xr2_x1 PORT MAP ( vss => vss, vdd => vdd, q => aux627_a, i1 => auxreg3, i0 => auxreg2); aux626_a : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => aux626_a, i1 => auxreg3, i0 => auxsc956); aux623_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux623_a, i1 => auxsc106, i0 => auxreg6); aux622_a : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => aux622_a, i1 => aux613_a, i0 => auxsc1322); aux615_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux615_a, i1 => auxsc10, i0 => auxreg3); aux613_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux613_a, i1 => auxreg3, i0 => auxsc14); aux611_a : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => aux611_a, i1 => auxreg5, i0 => aux597_a); aux609_a : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => aux609_a, i1 => auxreg6, i0 => scout); aux605_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux605_a, i1 => aux590_a, i0 => auxreg3); aux603_a : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq =% 3E aux603_a, i1 => scout, i0 => auxreg3); aux601_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux601_a, i1 => auxreg3, i0 => auxsc102); aux600_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux600_a, i1 => auxsc6, i0 => auxreg6); aux597_a : o2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux597_a, i1 => auxreg3, i0 => auxsc1320); aux595_a : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => aux595_a, i1 => auxreg2, i0 => auxsc7); aux592_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux592_a,% 0D i1 => aux591_a, i0 => auxsc27); aux591_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux591_a, i1 => aux590_a, i0 => auxsc7); aux590_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux590_a, i1 => auxsc6, i0 => scout); aux588_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux588_a, i1 => auxreg3, i0 => auxsc1232); aux587_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux587_a, i1 => auxreg2, i0 => auxsc10); aux583_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux583_a, i1 =% 3E aux582_a, i0 => auxreg3); aux582_a : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => aux582_a, i1 => auxreg2, i0 => scout); aux580_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux580_a, i1 => aux578_a, i0 => auxreg3); aux579_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux579_a, i1 => auxsc102, i0 => auxsc7); aux578_a : nxr2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => aux578_a, i1 => auxreg2, i0 => scout); aux577_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux577_a, i1 => aux576_a%2 C i0 => auxsc352); aux576_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux576_a, i1 => aux568_a, i0 => auxsc27); aux573_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux573_a, i1 => aux567_a, i0 => auxsc7); aux570_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux570_a, i1 => auxreg3, i0 => auxreg2); aux569_a : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => aux569_a, i1 => auxreg3, i0 => auxreg2); aux568_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux568_a, i1 => aux567_a, i0 => auxreg3); aux567_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux567_a, i1 => auxreg2, i0 => scout); aux566_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux566_a, i1 => scout, i0 => auxreg3); aux564_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux564_a, i1 => auxreg7, i0 => auxreg6); ef_1 : noa2a22_x1 PORT MAP ( vss => vss, vdd => vdd, nq => ef_1, i3 => auxsc1647, i2 => auxsc1646, i1 => auxsc171, i0 => test); aux729_a : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => aux729_a% 2C i1 => auxreg5, i0 => auxreg4); aux731_a : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => aux731_a, i1 => auxreg6, i0 => auxreg5); aux732_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux732_a, i1 => auxreg6, i0 => auxreg5); aux733_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux733_a, i1 => auxreg7, i0 => auxsc128); aux736_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux736_a, i1 => auxreg5, i0 => auxreg4); aux737_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux737_a, i 1 => auxsc423, i0 => auxreg5); aux738_a : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => aux738_a, i1 => auxreg5, i0 => auxsc423); aux740_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux740_a, i1 => auxsc423, i0 => auxreg7); aux742_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux742_a, i1 => aux729_a, i0 => auxreg6); aux752_a : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => aux752_a, i1 => auxreg7, i0 => auxreg4); aux757_a : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => aux757_a, i1 =% 3E ir_opcod(17), i0 => ir_opcod(16)); aux758_a : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux758_a, i1 => aux757_a, i0 => auxsc21); aux762_a : no2_x1 PORT MAP ( vss => vss, vdd => vdd, nq => aux762_a, i1 => ir_opcod(15), i0 => ir_opcod(14)); aux765_a : a3_x2 PORT MAP ( vss => vss, vdd => vdd, q => aux765_a, i2 => auxsc47, i1 => auxsc46, i0 => ir_opcod(4)); ep_6 : sff1_x4 PORT MAP ( vss => vss, vdd => vdd, q => scout, i => auxsc276, ck => ck); ep_5 : sff1_x4 PORT MAP ( vss => vss, vdd => vdd% 2C q => auxreg2, i => auxsc666, ck => ck); ep_4 : sff1_x4 PORT MAP ( vss => vss, vdd => vdd, q => auxreg3, i => auxsc970, ck => ck); ep_3 : sff1_x4 PORT MAP ( vss => vss, vdd => vdd, q => auxreg4, i => auxsc1207, ck => ck); ep_2 : sff1_x4 PORT MAP ( vss => vss, vdd => vdd, q => auxreg5, i => auxsc1437, ck => ck); ep_1 : sff1_x4 PORT MAP ( vss => vss, vdd => vdd, q => auxreg6, i => ef_1, ck => ck); ep_0 : sff1_x4 PORT MAP ( vss => vss, vdd => vdd, q => auxreg7, i => auxsc169 6, ck => ck); end VST; Finger Information : -------------------- [enseig.lip6.fr] Login name: dea9194 In real life: MIPS 1 [Roselyne] Directory: /users/dsk04/dea9194 Shell: /asim/gnu/bin/tcsh Never logged in. No unread mail No Plan. End Alliance bug report 1.3

 



Alliance Web Site © 1997, 2002 ASIM/LIP6/UPMC, page maintained by Czo [Olivier Sirol] , last updated on 22 March 2001.