I've just finished building a single-cycle processor based on the Patterson & Hennesy book. Every component is Ok, but now I have to test the whole thing. I don't know what's the standard procedure to do so. I've thought about filling my instruction ROM and data RAM using mips_asm and then running asimut, but I don't know how to validate the results. I'd like to know if it is possible to have a dump of the internal state of my register bank and memory after each cycle. Thanks in advance. Mario Bergotto.