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Name

tpl - LV500 Template description format.

Origin

This software belongs to the ALLIANCE CAD system from the CAO-VLSI team at ASIM/LIP6/UPMC laboratory.
LIP6/ASIM
University P. et M. Curie 4, place Jussieu 75252 PARIS Cedex 05 FRANCE
Fax : {33/0} 1.44.27.62.86
E-mail support : alliance-support@asim.lip6.fr

Description

The TPL format is used by patest with PAT format to produce a MSA file readable by the LV500 tester. It provides two types of informations:

- Timing characteristics of the pattern file.
- Wiring description of the chip.

the Format

Timing characteristics
First, clock signal must be declared using a declaration of the form:

CLOCK input_output_name [format] ;

where format is either R0 (default value) or R1. R0 represents an active HIGH signal, and R1 an active LOW signal. There can be severals clock signals.

Then each combination of the clock signals in the pattern file must be associated with 5 timing indications in nano-seconds. The order in wich this 5 timing indications are described is indicated in a line of the form:

PARAM CYCLE DELAY WIDTH FORCE COMPARE ;

This line if followed by the timing indications associated to each combination of the clock signals :

PHASE <phase_description> time1 time2 time3 time4 time5 ;

The signification of each timing indication is :

CYCLE
The pattern length.
DELAY
The time when clock signals rise (or fall) from the beginning

of the pattern.

WIDTH
The length of the high (or low) state of clock signals.
FORCE
The time when inputs signals change their values from the beginning of the pattern.
COMPARE
The time when outputs are checked from the beginning of the pattern.

Wiring description
Each logical connector of the chip must be associated with its physical sector and channel on the tester using :

PIN <input_output_name> <sector>.<channel> ;

All the logical connector must be listed here. The list is end whith a end ; statement.

Example

## My circuit is a latch design, with two clocks ## active high: the master clock and the slave clock CLOCK ckm R0;
CLOCK cks R0;

## In my pattern file, I cannot find a combination ## of ckm/cks different from the two following one : ## `10' : loading master latches
## `01' : loading slave latches

PARAM
CYCLE DELAY WIDTH FORCE COMPARE ; PHASE `10' 200 50 100 10 160 ; PHASE `01' 200 40 50 10 160 ;

## my chip is a 7 pin chip.
PIN ckm 0.0 ;
PIN cks 0.a ;
PIN in1 0.f ;
PIN in2 1.1 ;
PIN out 0.b ;
PIN vdd 3.0 ;
PIN vss 0.c ;
end ;

See Also

patest(1) , pat(5)

Bug Report

This tool is under development at the ASIM/LIP6/UPMC laboratory, cao-vlsi research team.
We need your feedbak to improve documentation and tools. If you find bugs, please fill-in the form at http://asim.lip6.fr/alliance/support/bug-report/ Thanks for doing this.


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