alliance-support '2000
Re: probleme de vasy


Ludovic JACOMME (Ludovic.JACOMME@asim.lip6.fr)
Wed, 8 Mar 2000 09:39:04 +0100

Hi, Please post this question on the alliance-support mailing list. I inform you that i won't answer your questions any more if you send them directly to my personnal mail address. I'm not the support manager of Alliance (Like Mr Olivier Sirol), i'm just the author or co-author of serveral tools in Alliance. VASY doesn't support for the moment, structural descriptions and packages ... That's why, your design can't be compiled by VASY. (Have a look on the man page vasy(8), as i told you SEVERAL times, one month ago) On Tue, Mar 07, 2000 at 04:58:28AM -0800, david hasan wrote: > bonjour Mr JACOMME > > nous voulons utilser le tool vasy pour synthetiser le mips 6502.vbe > a prtir d'un 6502.vhd .mais a chaque fois il signale"bad entity declaration > " et "parse error pour les bibliotheques". > voici 6502.vhd: > library ieee;^M > use ieee.std_logic_1164.all;^M > use ieee.std_logic_arith.all;^M > use ieee.std_logic_unsigned.all;^M > library work;^M > > 37 package free_6502 is^M > 38 component core_6502^M > 39 port (clk :in std_logic;^M > 40 reset :in std_logic;^M > 41 irq_in :in std_logic;^M > 42 nmi_in :in std_logic;^M > 43 addr_pin :out std_logic_vector (15 downto 0);^M > 44 din :in std_logic_vector (7 downto 0);^M > 45 dout :out std_logic_vector (7 downto 0);^M > 46 dout_oe :out std_logic;^M > 47 we_pin :out std_logic;^M > 48 rd_pin :out std_logic;^M > 49 sync :out std_logic^M > 50 );^M > 51 end component;^M > 52 ^M > 53 component core_6502_debug^M > 54 port (clk :in std_logic;^M > 55 reset :in std_logic;^M > 56 irq_in :in std_logic;^M > 57 nmi_in :in std_logic;^M > 58 addr_pin :out std_logic_vector (15 downto 0);^M > 59 din :in std_logic_vector (7 downto 0);^M > 60 dout :out std_logic_vector (7 downto 0);^M > 61 dout_oe :out std_logic;^M > 62 we_pin :out std_logic;^M > 63 rd_pin :out std_logic;^M > 64 sync :out std_logic;^M > 65 stack_page :in std_logic_vector (7 downto 0);^M > 66 reg_a_out :out std_logic_vector (7 downto 0);^M > 67 reg_x_out :out std_logic_vector (7 downto 0);^M > 68 reg_y_out :out std_logic_vector (7 downto 0);^M > 69 reg_sr_out :out std_logic_vector (7 downto 0);^M > 70 reg_sp_out :out std_logic_vector (7 downto 0);^M > 71 reg_pc_out :out std_logic_vector (15 downto 0)^M > 72 );^M > 73 end component;^M > 74 end free_6502;^M > 75 ^M > 76 > ------------------------------------------------------------------------ > --^M > 77 > ------------------------------------------------------------------------ > --^M > 78 library ieee;^M > 79 use ieee.std_logic_1164.all;^M > 80 use ieee.std_logic_arith.all;^M > 81 use ieee.std_logic_unsigned.all;^M > 82 library work;^M > 83 use work.microcode.all;^M > 84 use work.free_6502.all;^M > 85 ^M > 86 ^M > 87 entity core_6502_debug is^M > 88 port (clk :in std_logic;^M > 89 reset :in std_logic;^M > 90 irq_in :in std_logic;^M > 91 nmi_in :in std_logic;^M > 92 addr_pin :out std_logic_vector (15 downto 0);^M > 93 din :in std_logic_vector (7 downto 0);^M > 94 dout :out std_logic_vector (7 downto 0);^M > 95 dout_oe :out std_logic;^M > 96 we_pin :out std_logic;^M > 97 rd_pin :out std_logic;^M > 98 sync :out std_logic;^M > 99 stack_page :in std_logic_vector (7 downto 0);^M > 100 reg_a_out :out std_logic_vector (7 downto 0);^M > 101 reg_x_out :out std_logic_vector (7 downto 0);^M > 102 reg_y_out :out std_logic_vector (7 downto 0);^M > 103 reg_sr_out :out std_logic_vector (7 downto 0);^M > 104 reg_sp_out :out std_logic_vector (7 downto 0);^M > 105 reg_pc_out :out std_logic_vector (15 downto 0)^M > 106 );^M > 107 end core_6502_debug;^M > 108 ^M > 109 ^M > 110 architecture core_6502_arch_debug of core_6502_debug is^M > 111 Constants^M > 112 constant reset_opcode :std_logic_vector (7 downto 0) := > "00000011";^M > 113 constant irq_opcode :std_logic_vector (7 downto 0) := > "01000011";^M > 114 constant nmi_opcode :std_logic_vector (7 downto 0) := > "00110011";^M > 115 constant vect_nmi1 :std_logic_vector (15 downto 0) := > "111111111111 > 1010";^M > 116 constant vect_nmi2 :std_logic_vector (15 downto 0) := > "111111111111 > 1011";^M > 117 constant vect_reset1 :std_logic_vector (15 downto 0) := > "111111111111 > 1100";^M > 118 constant vect_reset2 :std_logic_vector (15 downto 0) := > "111111111111 > 1101";^M > 119 constant vect_irq1 :std_logic_vector (15 downto 0) := > "111111111111 > 1110";^M > 120 constant vect_irq2 :std_logic_vector (15 downto 0) := > "111111111111 > 1111";^M > 121 ^M > 122 Internal state info^M > 123 type STATES is (RESET1, RESET2, FETCH, START_IRQ, START_NMI, > RUN);^M > 124 signal state :STATES;^M > 125 signal step :std_logic_vector (2 downto 0);^M > 126 ^M > 127 registered inputs^M > 128 signal nmi_reg1 :std_logic;^M > 129 signal nmi_reg2 :std_logic;^M > 130 signal irq_reg :std_logic;^M > 131 signal data_in :std_logic_vector (7 downto 0);^M > 132 ^M > 133 Microcode ROM outputs^M > 134 signal done :MCT_DONE;^M > 135 signal addr_op :MCT_ADDR_OP;^M > 136 signal din_le :MCT_DIN_LE;^M > 137 signal rd_en :MCT_RD_EN;^M > 138 signal dout_op :MCT_DOUT_OP;^M > 139 signal dint1_op :MCT_DINT1_OP;^M > 140 signal dint2_op :MCT_DINT2_OP;^M > 141 signal dint3_op :MCT_DINT3_OP;^M > 142 signal pc_op :MCT_PC_OP;^M > 143 signal sp_op :MCT_SP_OP;^M > 144 signal alu1 :MCT_ALU1;^M > 145 signal alu2 :MCT_ALU2;^M > 146 signal alu_op :MCT_ALU_OP;^M > 147 signal a_le :MCT_A_LE;^M > 148 signal x_le :MCT_X_LE;^M > 149 signal y_le :MCT_Y_LE;^M > 150 signal flag_op :MCT_FLAG_OP;^M > 151 ^M > 152 Internal registers^M > 153 signal a_reg :std_logic_vector (7 downto 0);^M > 154 signal x_reg :std_logic_vector (7 downto 0);^M > 155 signal y_reg :std_logic_vector (7 downto 0);^M > 156 signal dint1 :std_logic_vector (7 downto 0);^M > 157 signal dint2 :std_logic_vector (7 downto 0);^M > 158 signal dint3 :std_logic_vector (7 downto 0);^M > 159 signal opcode_reg :std_logic_vector (7 downto 0);^M > 160 signal sp :std_logic_vector (7 downto 0);^M > 161 signal pc :std_logic_vector (15 downto 0);^M > 162 signal n_flag :std_logic;^M > 163 signal v_flag :std_logic;^M > 164 signal b_flag :std_logic;^M > 165 signal d_flag :std_logic;^M > 166 signal i_flag :std_logic;^M > 167 signal z_flag :std_logic;^M > 168 signal c_flag :std_logic;^M > 169 ^M > 170 Combinotorial signals^M > 171 signal opcode :std_logic_vector (7 downto 0);^M > 172 signal alu_in1 :std_logic_vector (8 downto 0);^M > 173 signal alu_in2 :std_logic_vector (8 downto 0);^M > 174 signal alu_out :std_logic_vector (8 downto 0);^M > 175 ^M > 176 signal alu_add :std_logic_vector (8 downto 0);^M > 177 signal alu_add_in2 :std_logic_vector (8 downto 0);^M > 178 signal alu_add_cin :std_logic;^M > 179 ^M > 180 signal addr_out_d :std_logic_vector(15 downto 0);^M > 181 ^M > 182 Misc signals^M > 183 signal first_run :std_logic;^M > 184 signal fetch_d :std_logic;^M > 185 signal data_out :std_logic_vector (7 downto 0);^M > 186 signal data_oe :std_logic;^M > 187 signal addr_out :std_logic_vector (15 downto 0);^M > 188 signal we_out :std_logic;^M > 189 signal nmi_event :std_logic;^M > 190 ^M > 191 begin^M > 192 Debug outputs^M > 193 reg_a_out <= a_reg;^M > 194 reg_x_out <= x_reg;^M > 195 reg_y_out <= y_reg;^M > 196 reg_sr_out <= n_flag & v_flag & '1' & b_flag & d_flag^M > 197 & i_flag & z_flag & c_flag;^M > 198 reg_sp_out <= sp;^M > 199 reg_pc_out <= pc;^M > 200 ^M > 201 ^M > 202 The sync output^M > 203 process (clk, reset)^M > 204 begin^M > 205 if reset='1' then^M > 206 sync <= '0';^M > 207 elsif clk'event and clk='1' then^M > 208 case state is^M > 209 when RESET1 => sync <= '0';^M > 210 when RESET2 => sync <= '0';^M > 211 when FETCH => sync <= '0';^M > 212 when START_IRQ => sync <= '0';^M > 213 when START_NMI => sync <= '0';^M > 214 when RUN =>^M > 215 if done=MC_DONE then^M > 216 if nmi_event='1' then^M > 217 sync <= '0';^M > 218 elsif i_flag='0' and irq_reg='1' then^M > 219 sync <= '0';^M > 220 else^M > 221 sync <= '1';^M > 222 end if;^M > 223 end if;^M > 224 when others => sync <= '0'; ^M > 225 end case;^M > 226 end if;^M > 227 end process;^M > 228 ^M > 229 ^M > 230 The main state machine^M > 231 process (clk, reset)^M > 232 begin^M > 233 if reset='1' then^M > 234 state <= RESET1;^M > 235 elsif clk'event and clk='1' then^M > 236 case state is^M > 237 when RESET1 => state <= RESET2;^M > 238 when RESET2 => state <= RUN;^M > 239 when FETCH => state <= RUN;^M > 240 when START_IRQ => state <= RUN;^M > 241 when START_NMI => state <= RUN;^M > 242 when RUN =>^M > 243 if done=MC_DONE then^M > 244 if nmi_event='1' then^M > 245 state <= START_NMI;^M > 246 elsif i_flag='0' and irq_reg='1' then^M > 247 state <= START_IRQ;^M > 248 else^M > 249 state <= FETCH;^M > 250 end if;^M > 251 end if;^M > 252 when others => state <= RESET1;^M > 253 end case;^M > 254 end if;^M > 255 end process;^M > 256 ^M > 257 ^M > 258 The microcode step counter^M > 259 process (clk, reset)^M > > ........etc etc > > merci de votre aide > > > > > ______________________________________________________ > Get Your Private, Free Email at http://www.hotmail.com (_) ___ Ludovic JACOMME _ _ ( ) ( ) ( ) ( 6 ) Laboratoire LIP6, Equipe ASIM ( ) (_) ( _ ) Couloir 55-65, 2eme etage, ( )___ ( ) Universite P. et M. Curie (P6) (_____) (_) 4 place Jussieu, 75252 Paris Cedex 05 Tel: (33) 01.44.27.54.15 Fax: (33) 01.44.27.72.80 ICQ: 62526530 mailto: Ludovic.Jacomme@asim.lip6.fr http: //asim.lip6.fr/~ludo

 



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