Hello sirs, I was doing something(a code converter) relating to finite state machines. Using the Meally configuration, I wrote my code.fsm. Visualization and synthesis of my code did not yeild any errors. I wrote and applied a pattern file to my design and upon viewing the results (r1.pat) I noticed that the output changes even when clk = 0., for example: Heres a line of my r1.pat file: (where ck = clock, r = reset, x is my input, and z is my output) -- Pattern description : -- v v c r x z -- d s k -- d s < 0 ps>pat_0 : 1 0 0 1 0 ?0 ; < 1 ps>pat_1 : 1 0 1 1 1 ?0 ; < 2 ps>pat_2 : 1 0 0 1 0 ?0 ; < 3 ps>pat_3 : 1 0 1 1 0 ?0 ; < 4 ps>pat_4 : 1 0 0 1 0 ?0 ; < 5 ps>pat_5 : 1 0 1 1 1 ?0 ; < 6 ps>pat_6 : 1 0 0 1 0 ?0 ; < 7 ps>pat_7 : 1 0 1 1 0 ?0 ; < 8 ps>pat_8 : 1 0 0 0 0 ?1 ; < 9 ps>pat_9 : 1 0 1 0 0 ?1 ; < 10 ps>pat_10 : 1 0 0 0 0 ?1 ; < 11 ps>pat_11 : 1 0 1 0 0 ?0 ; Ofcourse when reset = 1, z = 0 regardless of the values of 'x', therefore lines 0 to 7(above) are correct. However, in line 8, even where ck = 0, and reset = 0, the output z = 1. Pls why is this so. I suppose that when ck = 0, the output should retain its previous value. The ck procedure I used is: PROCESS ( ck ) BEGIN IF ( ck = '1' AND NOT ck'STABLE ) THEN CURRENT_STATE <= NEXT_STATE; END IF; END PROCESS; I suppose the above process means that the output should change only at the rising edge of the clock pulse. As a result of line#8, all the succeeding lines in the output are wrong. I checked my fsm code. There was nothing wrong in it. PLS HELP Giie --------------------------------- Do You Yahoo!? Yahoo! Auctions Great stuff seeking new owners! Bid now!