Cicuttin Andres wrote: > > Dear Alliance support team, > > We are trying to run an exercise using Data Path Entities, it is a > simple 4-bit adder accumulator. This exercises run well on the previous > releases of alliance but now we are in trouble trying to run it with the > new Alliance3.2b. We modified the original fpgen changing the third line > were the variable TOP is defined. We put the correct PATH for our case and > fpgen start working, but still there are problems... I'm forwarding to alliance-support some answers so that this mail is logged... > From Ludovic.Jacomme@asim.lip6.fr Wed Oct 14 17:29:20 1998 > Subject: Re: Urgent Help > To: hakimus@univalle.edu.co (Luis A. Caceres) > Date: Wed, 14 Oct 1998 17:29:20 +0200 (MET DST) > > > > Hi all, > > > > I am beginner with VHDL-Alliance, and have some problems for to invoke > > custom circuit in another circuit. > > > > I have described one full adder (myFullAdder.vbe = two output's ). > > Now I need to describe one circuit that invoke my full adder, > > as one component. > > > > The question is: how can I get that alliance to recognize my circuit? > > How can I to define my circuit ? and later call it as one component? > > > > Example: > > entity circuit is > > port ( A, B,C: in BIT; > > X,Y: out BIT); > > end; > > > > architecture STRUCTURE of circuit is > > component myFullAdder <----------- This is the problem: > > port (A,B,C: in BIT; myFullAdder > > is not Scell, > > X,Y: out BIT); How I get > > that Alliance recognize it? > > end component; > > > > begin > > ...structural description... > > end; > > > > Thank in advance by your help!!!!! > > > > Luis A. Caceres. > > > > PD: Please help me, I not have another resource. > > > > > Hi ! > > I suggest you to have a look on the tutorial of the addaccu. > If you want to use your component myFullAdder in the structural view > of your circuit you have to write the behaviour of myFullAdder in a file > myfulladder.vbe. > I you want a physical view of your circuit you need to create a structural > view of your cell myFullAdder (with bop and scmap). > > Good luck Ludo. > 2-From: Denis Hommais <Denis.Hommais@asim.lip6.fr> 29/10/98 10:07 Hi, > MBK_CATA_LIB=.:/alliance/archi/Linux_elf/cells/sclib: > /alliance/archi/Linux_elf/cells/padlib: > /alliance/archi/Linux_elf/cells/fplib: > /alliance/archi/Linux_elf/cells/rsa > /* heterogeneous operator */ > LOINS ("ndrv_dp","CLKINV","CLK","NCLK","vdd","vss",0); ndrp_dp is a cell that comes from dplib. You will have better result adding /alliance/archi/Linux_elf/cells/dplib in your MBK_CATA_LIB. Denis. Thanks for your interest in Alliance. Sincerely, Olivier Sirol. ==================================================================== Olivier SIROL Alliance Team ASIM/LIP6/UPMC Coul. 55-65, 2e etg, Bur. 204 75252 Paris Cedex 05 mailto:alliance-support@asim.lip6.fr Tel: +33 1 44 27 53 24 http://asim.lip6.fr/alliance/ Fax: +33 1 44 27 72 80 ====================================================================