Begin Alliance bug report 1.3 ------------------------------------------------------------------- Posted on : 1998 April 15 (Wednesday at 12:34) MET DST by : bizjak@rd.iskraemeco.si subject : BUG scmap : ##### WARNING : 'mulb_ix_0' n'est pas un virtuel version : Alliance 3.2b ------------------------------------------------------------------- Problem description : --------------------- When I compile behavioral VHDL file, generated with bop, I got message, saying: ##### WARNING : 'mulb_ix_0' n'est pas un virtuel. I included bop' output file, which produces problem. Environnement : --------------- Platform : SunOS ems 5.5.1 Generic_103640-18 sun4c sparc SUNW,Sun_4_75 alliance=/software/shared/alliance/share/etc/env.csh TOP=/software/shared/alliance/archi/Solaris MBK_IN_LO=vst MBK_OUT_LO=vst MBK_IN_PH=ap MBK_OUT_PH=ap MBK_WORK_LIB=. MBK_CATAL_NAME=CATAL MBK_SCALE_X=10 VH_MAXERR=10 VH_BEHSFX=vbe VH_PATSFX=pat MBK_CATA_LIB=.:/software/shared/alliance/archi/Solaris/cells/sclib MBK_TARGET_LIB=/software/shared/alliance/archi/Solaris/cells/sclib MBK_C4_LIB=./cellsC4 XPAT_PARAM_NAME=/software/shared/alliance/archi/Solaris/etc/xpat.par XFSM_PARAM_NAME=/software/shared/alliance/archi/Solaris/etc/xfsm.par DREAL_TECHNO_NAME=/software/shared/alliance/archi/Solaris/etc/cmos_7.dreal GRAAL_TECHNO_NAME=/software/shared/alliance/archi/Solaris/etc/cmos_7.graal RDS_TECHNO_NAME=/software/shared/alliance/archi/Solaris/etc/cmos_7.rds RDS_IN=cif RDS_OUT=cif ELP_TECHNO_NAME=/software/shared/alliance/archi/Solaris/etc/prol10.elp How to reproduce the bug : -------------------------- -- VHDL data flow description generated from `xxx` -- date : Wed Apr 15 11:55:57 1998 -- Entity Declaration ENTITY xxx IS PORT ( mula : in bit_vector(3 DOWNTO 0) ; -- mula mulb : in bit_vector(3 DOWNTO 0) ; -- mulb mulr : out bit_vector(7 DOWNTO 0) ; -- mulr load : in BIT; -- load clk : in BIT -- clk ); END xxx; -- Architecture Declaration ARCHITECTURE VBE OF xxx IS SIGNAL xleft : REG_VECTOR(7 DOWNTO 0) REGISTER; -- xleft SIGNAL xright : REG_VECTOR(3 DOWNTO 0) REGISTER; -- xright SIGNAL ra_cw_1 : BIT; -- ra_cw_1 SIGNAL ra_cw_2 : BIT; -- ra_cw_2 SIGNAL ra_cw_3 : BIT; -- ra_cw_3 SIGNAL ra_cw_4 : BIT; -- ra_cw_4 SIGNAL ra_cw_5 : BIT; -- ra_cw_5 SIGNAL ra_cw_6 : BIT; -- ra_cw_6 SIGNAL xright_l_0 : BIT; -- xright_l_0 SIGNAL xright_l_1 : BIT; -- xright_l_1 SIGNAL xright_l_2 : BIT; -- xright_l_2 SIGNAL xright_l_3 : BIT; -- xright_l_3 SIGNAL xleft_l_0 : BIT; -- xleft_l_0 SIGNAL xleft_l_1 : BIT; -- xleft_l_1 SIGNAL xleft_l_2 : BIT; -- xleft_l_2 SIGNAL xleft_l_3 : BIT; -- xleft_l_3 SIGNAL xleft_l_4 : BIT; -- xleft_l_4 SIGNAL xleft_l_5 : BIT; -- xleft_l_5 SIGNAL xleft_l_6 : BIT; -- xleft_l_6 SIGNAL xleft_l_7 : BIT; -- xleft_l_7 SIGNAL mulb_ix_0 : BIT; -- mulb_ix_0 SIGNAL mulb_ix_1 : BIT; -- mulb_ix_1 SIGNAL mulb_ix_2 : BIT; -- mulb_ix_2 SIGNAL mulb_ix_3 : BIT; -- mulb_ix_3 SIGNAL mulb_ii_0 : BIT; -- mulb_ii_0 SIGNAL mulb_ii_1 : BIT; -- mulb_ii_1 SIGNAL mulb_ii_2 : BIT; -- mulb_ii_2 SIGNAL mulb_ii_3 : BIT; -- mulb_ii_3 SIGNAL mulb_i_0 : BIT; -- mulb_i_0 SIGNAL mulb_i_1 : BIT; -- mulb_i_1 SIGNAL mulb_i_2 : BIT; -- mulb_i_2 SIGNAL mulb_i_3 : BIT; -- mulb_i_3 SIGNAL mula_ix_0 : BIT; -- mula_ix_0 SIGNAL mula_ix_1 : BIT; -- mula_ix_1 SIGNAL mula_ix_2 : BIT; -- mula_ix_2 SIGNAL mula_ix_3 : BIT; -- mula_ix_3 SIGNAL mula_ii_0 : BIT; -- mula_ii_0 SIGNAL mula_ii_1 : BIT; -- mula_ii_1 SIGNAL mula_ii_2 : BIT; -- mula_ii_2 SIGNAL mula_ii_3 : BIT; -- mula_ii_3 SIGNAL mula_i_0 : BIT; -- mula_i_0 SIGNAL mula_i_1 : BIT; -- mula_i_1 SIGNAL mula_i_2 : BIT; -- mula_i_2 SIGNAL mula_i_3 : BIT; -- mula_i_3 SIGNAL invt : BIT; -- invt BEGIN invt <= mulb (3); mula_i_3 <= (mula_ii_3 xor mula_ix_3); mula_i_2 <= (mula_ii_2 xor mula_ix_2); mula_i_1 <= (mula_ii_1 xor mula_ix_1); mula_i_0 <= (mula_ix_0 xor mula_ii_0); mula_ii_3 <= not (mula (3)); mula_ii_2 <= not (mula (2)); mula_ii_1 <= not (mula (1)); mula_ii_0 <= not (mula (0)); mula_ix_3 <= (mula_ii_2 and mula_ix_2); mula_ix_2 <= (mula_ii_1 and mula_ix_1); mula_ix_1 <= (mula_ix_0 and mula_ii_0); mula_ix_0 <= '1'; mulb_i_3 <= (mulb_ii_3 xor mulb_ix_3); mulb_i_2 <= (mulb_ii_2 xor mulb_ix_2); mulb_i_1 <= (mulb_ii_1 xor mulb_ix_1); mulb_i_0 <= (mulb_ix_0 xor mulb_ii_0); mulb_ii_3 <= not (mulb (3)); mulb_ii_2 <= not (mulb (2)); mulb_ii_1 <= not (mulb (1)); mulb_ii_0 <= not (mulb (0)); mulb_ix_3 <= (mulb_ii_2 and mulb_ix_2); mulb_ix_2 <= (mulb_ii_1 and mulb_ix_1); mulb_ix_1 <= (mulb_ix_0 and mulb_ii_0); mulb_ix_0 <= '1'; xleft_l_7 <= xleft_l_3; xleft_l_6 <= xleft_l_3; xleft_l_5 <= xleft_l_3; xleft_l_4 <= xleft_l_3; xleft_l_3 <= ((not (invt) and mula (3)) or (invt and mula_i_3)); xleft_l_2 <= ((not (invt) and mula (2)) or (invt and mula_i_2)); xleft_l_1 <= ((not (invt) and mula (1)) or (invt and mula_i_1)); xleft_l_0 <= ((not (invt) and mula (0)) or (invt and mula_i_0)); xright_l_3 <= ((not (invt) and mulb (3)) or (invt and mulb_i_3)); xright_l_2 <= ((not (invt) and mulb (2)) or (invt and mulb_i_2)); xright_l_1 <= ((not (invt) and mulb (1)) or (invt and mulb_i_1)); xright_l_0 <= ((not (invt) and mulb (0)) or (invt and mulb_i_0)); ra_cw_6 <= (('0' and xleft (5)) or (('0' or xleft (5)) and ra_cw_5)); ra_cw_5 <= (('0' and xleft (4)) or (('0' or xleft (4)) and ra_cw_4)); ra_cw_4 <= ((xright (3) and xleft (3)) or ((xright (3) or xleft (3)) and ra_cw_3)); ra_cw_3 <= ((xright (2) and xleft (2)) or ((xright (2) or xleft (2)) and ra_cw_2)); ra_cw_2 <= ((xright (1) and xleft (1)) or ((xright (1) or xleft (1)) and ra_cw_1)); ra_cw_1 <= ((xright (0) and xleft (0)) or ('0' and (xright (0) or xleft (0)))); label0 : BLOCK ((clk and not (clk'STABLE)) = '1') BEGIN xright (0) <= GUARDED (load and xright_l_0); END BLOCK label0; label1 : BLOCK ((clk and not (clk'STABLE)) = '1') BEGIN xright (1) <= GUARDED ((not (load) and xright (1)) or (load and xright_l_1)); END BLOCK label1; label2 : BLOCK ((clk and not (clk'STABLE)) = '1') BEGIN xright (2) <= GUARDED ((not (load) and xright (2)) or (load and xright_l_2)); END BLOCK label2; label3 : BLOCK ((clk and not (clk'STABLE)) = '1') BEGIN xright (3) <= GUARDED ((not (load) and xright (3)) or (load and xright_l_3)); END BLOCK label3; label4 : BLOCK ((clk and not (clk'STABLE)) = '1') BEGIN xleft (0) <= GUARDED (load and xleft_l_0); END BLOCK label4; label5 : BLOCK ((clk and not (clk'STABLE)) = '1') BEGIN xleft (1) <= GUARDED ((not (load) and xleft (1)) or (load and xleft_l_1)); END BLOCK label5; label6 : BLOCK ((clk and not (clk'STABLE)) = '1') BEGIN xleft (2) <= GUARDED ((not (load) and xleft (2)) or (load and xleft_l_2)); END BLOCK label6; label7 : BLOCK ((clk and not (clk'STABLE)) = '1') BEGIN xleft (3) <= GUARDED ((not (load) and xleft (3)) or (load and xleft_l_3)); END BLOCK label7; label8 : BLOCK ((clk and not (clk'STABLE)) = '1') BEGIN xleft (4) <= GUARDED ((not (load) and xleft (4)) or (load and xleft_l_4)); END BLOCK label8; label9 : BLOCK ((clk and not (clk'STABLE)) = '1') BEGIN xleft (5) <= GUARDED ((not (load) and xleft (5)) or (load and xleft_l_5)); END BLOCK label9; label10 : BLOCK ((clk and not (clk'STABLE)) = '1') BEGIN xleft (6) <= GUARDED ((not (load) and xleft (6)) or (load and xleft_l_6)); END BLOCK label10; label11 : BLOCK ((clk and not (clk'STABLE)) = '1') BEGIN xleft (7) <= GUARDED ((not (load) and xleft (7)) or (load and xleft_l_7)); END BLOCK label11; mulr (0) <= ('0' xor xright (0) xor xleft (0)); mulr (1) <= (xright (1) xor xleft (1) xor ra_cw_1); mulr (2) <= (xright (2) xor xleft (2) xor ra_cw_2); mulr (3) <= (xright (3) xor xleft (3) xor ra_cw_3); mulr (4) <= ('0' xor xleft (4) xor ra_cw_4); mulr (5) <= ('0' xor xleft (5) xor ra_cw_5); mulr (6) <= ('0' xor xleft (6) xor ra_cw_6); mulr (7) <= ('0' xor xleft (7) xor (('0' and xleft (6)) or (('0' or xleft (6)) and ra_cw_6))); END; Finger Information : -------------------- [rd.iskraemeco.si] End Alliance bug report 1.3