alliance-support '01
multiple answers to giie ....


Christophe Alexandre (Christophe.Alexandre@asim.lip6.fr)
Mon, 17 Dec 2001 14:34:15 +0100 (CET)

>Hi there, > > I'm trying to get familiar with netlist description etc. I wrote the code for a core description using the addaccu tutorial (core.c) as my guide. After writing the code, I generated the (.vst) etc, then applied the scr tool after which was nexlist extraction and comparison (lynx and lvx). > Here are two lines of my 'halfcore.c" file: > GENLIB_LOINS("xr2_y", "xr1", "x", "y", "sum", "vdd", "vss", 0); > GENLIB_LOINS("a2_y", "an1", "x", "y", "carry", "vdd", "vss", 0); > >Everything went well until the lvx comparison when I got the ff output: >$ lvx vst al halfcore halfcore > > @@@@@@ @@@@ @@@ @@@@ @@@@ > @@ @@ @ @@ @ > @@ @@ @ @@ @ > @@ @@ @ @@ @ > @@ @@ @ @@ > @@ @@ @ @@ > @@ @@ @ @@@ > @@ @@@ @ @@ > @@ @ @@@ @ @@ > @@ @ @ @ @@ > @@@@@@@@@@ @ @@@ @@@@ > > Gate Netlist Comparator > > Alliance CAD System 4.5.0, lvx 1.2 > Copyright (c) 1992-2001, ASIM/LIP6/UPMC > E-mail support: alliance-support@asim.lip6.fr > > > >***** Loading halfcore (vst)... > >***** Loading halfcore (al)... > > >***** Compare Terminals ........... >***** O.K. (0 sec) > >***** Compare Instances .......... >Instance 'an1' only in netlist 1 >Instance 'xr1' only in netlist 1 > >***** Netlists are NOT Identical! ***** (0 sec) > >Note that the netlists are not identical because of the two instance names( in bold ). How can I correct this kind of error - considering that the files compared (halfcore.vst and halfcore.al) are from the same file (halfcore.c). > Do you still have this error ?? Look to your halfcore.ap file generated by scr. What are the name of the instances in this file ? You can look at your placement with the tool graal. Look if your halfcore looks normal or if something went wrong. > > I keep on getting the error below(bold) when I invoke the RING command. Pls help: > >$ export MBK_CATA_LIB=$ALLIANCE_TOP/cells/padlib:$ALLIANCE_TOP/cells/sxlib >$ ring xverchip xverchip > > @@@@@@@ @ @@@@ @ > @@ @@ @@@ @@ @@ > @@ @@ @ @@ @ > @@ @@ @@@ @@@ @@ > @@ @@ @@@@ @@@ @ @@ > @@@@@ @@ @@ @@ @@ @@@@@ > @@ @@ @@ @@ @@ @@ @ @@ > @@ @@ @@ @@ @@ @@ @ @@ > @@ @@ @@ @@ @@ @@ @@ > @@ @@ @@ @@ @@ @@ @@ > @@@@@ @@@ @@@@@@ @@@@ @@@@ @@@@ > > PAD ring router > > Alliance CAD System 4.5.0, ring 2.11 > Copyright (c) 1991-2001, ASIM/LIP6/UPMC > E-mail support: alliance-support@asim.lip6.fr > > o reading netlists, layout views of core and pads. > o reading file of parameters, including the placements of pads. > o making equipotential list. > o making the first placement of pads. > o filling data internal structures. > o reading the connectors positions of the core. >Distance between connector <aout 2> and connector <enable> of the core isn't big > enough. > > >How do I correct such an error in my core. The genlib instruction does not give any errors when I generate core.vst. There is no relation between the GENLIB_LOINS instruction and placement. GENLIB_LOINS instantiates a logical model but there is no physical instruction with this. If you want to manually place your circuit. The genlib tool provides you with macros such as GENLIB_PLACE, GENLIB_PLACE_RIGHT, .... There are manuals for each macros. Look at the design you give to ring with graal maybe the placement of the connectors went wrong during the scr placement .... In that case you can change the connectors placement with a .scr file. Look at the manual of scr. Hope that will help... Christophe Alexandre

 



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