Table of Contents
rfg - register file generator
rfg
rfg -h
rfg bits words busses ro|rs|ds|ba
[ -ff ] [ -id ] [ -lp ] [ -wel|-weh ] [ -stuck ]
[ -virtual ] [ -msb0 ]
[ -layout ] [ -icon ] [ -vhdl ] [ -patterns ] [ -datasheet ]
[ -physical_box ] [ -logical_box ]
[ -o blockname ]
This software belongs to the ALLIANCE CAD system from the CAO-VLSI team at
ASIM/LIP6/UPMC laboratory.
LIP6/ASIM
University P. et M. Curie
4, place Jussieu
75252 PARIS Cedex 05
FRANCE
Fax : {33/0} 1.44.27.62.86
E-mail support : alliance-support@asim.lip6.fr
The first form is a short on line help.
The second is a long on line help.
In the last form, rfg is a register file generator for bit-sliced datapaths.
It generates differents views of a register file and offers a very
large range of possible parameters. The generator respect the CAO-VLSI
definition of a data-path. The slice is fixed to 60 lambdas, allows virtual
terminals and could be used with the data-path compiler fitpath(1)
.
The generator needs a leaf cell library to work well. The MBK_CATA_LIB(1)
environment variable should contain the path to the generator library,
rflib.
- -h
- long form help.
- bits
- Word size. The range is from 2 to 64, the value
must be even.
- words
- Number of registers. The range is from 2 to 256,
the value must be even.
- busses
- Number of read busses : 1 or 2. Generated
register file has one write address bus and one
or two read address busses.
- ro
- Generates a block without address decoders, with
an optimized width.
- rs
- Generates a block without address decoders, that
could be abutted with a decoders block.
- ds
- Generates a block that contains only the address
decoders. This block has the same size and the
same connectors interface as the block generated
with the rs option.
- ba
- Generates a complete register file with address
decoders.
- -ff
- Adds output latches then the generated register
file work like a edge triggered flip-flop rather
than a level sensitive latch.
- -id
- Inverts data polarity between input bus and output
busses.
- -lp
- Reduces consumption but increases read time. This
option is only available for register file which
have more than 16 registers.
- -wel
- Adds a write enable signal. The signal is active
low.
- -weh
- Adds a write enable signal. The signal is active
high.
- -stuck
- The register at address 0 will be stuck to a
value of 0.
- -virtual
- Generates a register file with virtual connectors,
as opposed to the default that generates
steady terminals, to be used by the data-path
compiler fitpath(1)
.
- -msb0
- Index 0 of vectorized busses will be used for the
most significant bit, else index 0 will be used
for the less significant bit of busses.
- -layout
- To obtain a layout view. The different formats
are given by mbk(1)
documentation.
- -icon
- To obtain a icon view.
- -vhdl
- To obtain a VHDL data-flow behavioral description
view.
- -patterns
- To obtain a patterns file.
- -datasheet
- To obtain a data sheet.
- -physical_box
- To obtain a physical outline view. Cannot be used
with the -layout option.
- -logical_box
- To obtain a netlist view. This view contains only
the logical block interface. The different formats
are given by mbk(1)
documentation.
- -o blockname
- blockname indicate the user name prefix for all
files generated. If no name is given, a default
name will be composed by the generator. For each
set of parameters and options, the default name
will be different.
Each terminal name is predefined and cannot not be modified by the user.
Index 0 could be the less significant bit or the most significant following
the msb option. N represent the number of bits of registers. M represent
the size of address busses, this size depend on number of registers.
Terminal names are :
- ad_w[0]-ad_w[M-1]
- Write address
- we
- Write enable signal
- ad_r_a[0]-ad_r_a[M-1]
- First read address
- ad_r_b[0]-ad_r_b[M-1]
- Second read address
- ck_m
- Clock signal
- in_a[0]-in_a[N-1]
- Data input
- out_a[0]-out_a[N-1]
- First data output
- out_b[0]-out_b[N-1]
- Second data output
- vdd, vss
- Power supplies
The complete register file dimension are approximately :
width = words * 34 lambdas.
height = (bits + 3 * busses + 6) * 60 lambdas.
The data sheet contains information on register file timings. These
informations are only available for complete register file (ba option).
Common timings for all register file :
- tc1
- Minimun width for clock high level.
- tc0
- Minimun width for clock low level.
- taws
- Minimum set up time for write address bus before clock rising
front.
- tawh
- Minimum hold time for write address bus after clock falling
front.
- tdts
- Minimum set up time for data input bus before clock falling
front.
- tdth
- Minimum hold time for data input bus after clock falling front.
Additionnal timings for level sensitive latch register file :
- trda
- Maximun read access time from read address bus stabilization to
data output (when write address is not equal to read address or
when clock is at low level).
- tpd
- Maximum propagation delay from data in bus stabilization to data
ouput bus (when write address is equal to read address and clock
is at high level).
Additionnal timings for edge triggered flip-flop register file :
- tars
- Minimum set up time for read address bus before clock falling
front.
- tarh
- Minimum hold time for read address bus before clock rising
front.
- toe
- Maximun read access time from clock falling front to data output.
rfg 24 16 2 rs -o my_reg -physical_box
Produces the outline view of 16 registers of 24 bits with 2 read
busses. The generated file name is my_reg.xx".
rfg 16 32 1 ba -wel -o test -layout -vhdl
Produces the layout and vhdl views of a 32 registers of 16 bits
complete register file with 1 read bus and a write enable input
active at low level. The prefix name of all generated files is
test".
- name.xx
- Layout, physical_box and logical_box views. For
these views, the suffixes depend on the
MBK_OUT_PH(1)
and MBK_OUT_LO(1)
environment variables.
The name is either the user name entered
under the -o option, or an internally generated
name, as explained under the OPTIONS section.
- name.icn
- Icon view.
- name.vbe
- vhdl behavior.
- name.pat
- Set of patterns for validation.
- MBK_CATA_LIB
- contains the directory path of the register file
generator leaf cell library. This library is by
default in /labo/cells/rfg", and if not, depends
upon the system administrator installation.
- MBK_WORK_LIB
- contains the directory path of the working directory,
usually set to .".
- MBK_IN_PH
- contains the format of the register file generator
leaf cell library.
- MBK_OUT_PH
- contains the expected format of the generated
layout.
- MBK_OUT_LO
- contains the expected format of the netlist output.
- MBK_CATA_LIB(1)
,
- MBK_WORK_LIB(1)
, MBK_IN_PH(1)
, MBK_OUT_PH(1)
,
MBK_OUT_LO(1)
, mbk(1)
, genlib(1)
, vhdl(1)
, fitpath(1)
, bsg(1)
, grog(1)
,
rsa(1)
.
This tool is under development at the ASIM/LIP6/UPMC laboratory, cao-vlsi
research team.
We need your feedbak to improve documentation and tools.
If you find bugs, please fill-in the form at
http://asim.lip6.fr/alliance/support/bug-report/
Thanks for doing this.
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page maintained by Czo [Olivier Sirol]
, last updated on 26 May 2000.