vbe
VHDL behavioural subset.
This software belongs to the ALLIANCE CAD system from the CAO-VLSI team at
ASIM/LIP6/UPMC laboratory.
LIP6/ASIM
University P. et M. Curie
4, place Jussieu
75252 PARIS Cedex 05
FRANCE
Fax : {33/0} 1.44.27.62.86
E-mail support : alliance-support@asim.lip6.fr
This document describes the ALLIANCE VHDL subset for behavioural data flow descriptions.
Allowed conncurrent statements are:
simple signal assignment
conditional signal assignment
selected signal assignment
concurrent assert statement
block statement
The above constraint may be felt as a hard restriction when designing distributed controled hardware (precharged line, distributed multiplexer, etc ...). To hurdle this, VHDL uses a special feature: guarded-resolved signals.
A resolved signal is a signal declared with a resolved subtype (see vhdl(5) ). A resolved subtype is a type combined with a resolution function. A resolved signal can be assigned by multiple signal assignments. Depending on the value of each driver, the resolution function determines the effective value of the signal.
A guarded signal is a resolved signal with drivers that can be disconntected. A guarded signal must be assigned inside a block statement through a guarded signal assignment.
A distributed multiplexer may be described as :
signal Distributed_Mux : mux_bit bus;
begin
first_driver_of_mux : block (Sel1 = `1')
begin
Distributed_Mux <= guarded Data1;
end block;
second_driver_of_mux : block (Sel2 = `1')
begin
Distributed_Mux <= guarded Data2;
end block;
LATCHES and REGISTERS
Sequential elements must be explicitly declared using the type reg_bit or
reg_vector (and must be of kind register). A sequential element must be
assigned inside a block statement by a guarded signal assignment.
Falling edge triggered D flip flop :
signal Reg : reg_bit register;
begin
flip_flop : block (ck = `0' and not ck'STABLE)
begin
Reg <= guarded Din;
end block;
Level sensitive latch:
signal Reg : reg_bit register;
begin
latch : block (ck = `1')
begin
Lat <= guarded D;in
end block;
In both cases, the guard expression must depend only on one signal if the description is to be processed by the logic synthetizer (bop + scmap).
The following operators are only supported: not, and, or, xor, nor, nand, &, =, /=
They can be applied on all types supported by the subset. Other standard VHDL operators (+, -, >, <, ...) have not been implemented in the present release.
Detailed timing information is not available at design time (cases a and b).
For an extracted netlist (case c) the detailed timing analysis is performed by a specific tool: the static timing analyser TAS (not delivered in the present version of ALLIANCE).
Thus, timing specification is not supported by the ALLIANCE VHDL subset. Simulation is performed in zero delay mode.
Assert statements are ignored by the logic synthesis tool.
An output can be assigned to the value `D' (don't care). This is taken into account by the logic synthesis tool in the optimization process. When the value of an output is `D' the logic synthesis tool may turn it into a `1' or a `0'.
A `D' value is understood as a `0' by the logic simulator (asimut).
Here is the description of an adder with an accumulator register.
entity add_accu is
port (
architecture data_flow of add_accu is
signal eff_data : bit_vector (31 downto 0); -- effective operande
constant initialize : bit := `0';
constant accumulate : bit := `1';
begin
with command select
eff_data <= X"0000_0000 when initialize,
write : block (clk = `0' and not clk'STABLE)
begin
accum_reg <= guarded adder_out;
end block;
cry_out <= adder_cry (32);
assert (vdd = `1' and vss = `0')
report power sypply is missing"
severity ERROR;
end;
vhdl(5) , vst(5) , bop(1) , glop(1) , scmap(1) , c4map(1) , asimut(1) , proof(1) , yagle(1)
This tool is under development at the ASIM/LIP6/UPMC laboratory, cao-vlsi
research team.
We need your feedbak to improve documentation and tools.
If you find bugs, please fill-in the form at
http://asim.lip6.fr/alliance/support/bug-report/
Thanks for doing this.