Alliance: A Complete CAD System for VLSI Design
Équipe Achitecture des Systèmes et Micro-Électronique
Laboratoire d'Informatique de Paris 6
Université Pierre et Marie Curie
4, Place Jussieu 75252 Paris Cedex 05,
France
alliance-support@asim.lip6.fr
VHDL behavioural subset
This document describes the ALLIANCE VHDL subset for
behavioural data flow descriptions.
CONCURRENT STATEMENTS
In a data flow architecture only concurrent statements
(except PROCESS
) are supported. All sequential statements
including loops, signal assignment, etc .. are to be banished.
Allowed conncurrent statements are:
- simple signal assignment
- conditional signal assignment
- selected signal assignment
- concurrent assert statement
BLOCK
statement
BUSES
When using concurrent statements, an ordinary signal can
be assigned only once. The value of the signal must be
explicitly defined by the signal assignment (for example,
in a selected signal assignment the value of the target
signal is to be defined for every value that the SELECT
expression can take).
The above constraint may be felt as a hard restriction
when designing distributed controled hardware (precharged
line, distributed multiplexer, etc ...). To hurdle this,
VHDL uses a special feature: guarded-resolved signals.
A resolved signal is a signal declared with a resolved
subtype. A resolved subtype is a type combined with a resolution
function. A resolved signal can be assigned by multiple signal
assignments. Depending on the value of each driver, the resolution
function determines the effective value of the signal.
A guarded signal is a resolved signal with drivers that
can be disconnected. A guarded signal must be assigned
inside a BLOCK
statement through a
GUARDED
signal assignment.
A distributed multiplexer may be described as :
SIGNAL Distributed_Mux : MUX_BIT BUS;
BEGIN
first_driver_of_mux : BLOCK ( Sel1 = '1' )
BEGIN
Distributed_Mux <= GUARDED Data1;
END BLOCK;
second_driver_of_mux : BLOCK ( Sel2 = '1' )
BEGIN
Distributed_Mux <= GUARDED Data2;
END BLOCK;
LATCHES and REGISTERS
Sequential elements must be explicitly declared using the
type REG_BIT
or REG_VECTOR
(and must
be of kind REGISTER
).
A sequential element must be assigned inside a BLOCK
statement by a GUARDED
signal assignment.
Falling edge triggered D flip flop:
SIGNAL Reg : REG_BIT REGISTER;
BEGIN
flip_flop : BLOCK ( ck = '0' AND NOT ck'STABLE )
BEGIN
Reg <= GUARDED Din;
END BLOCK;
Level sensitive latch:
SIGNAL Reg : reg_bit REGISTER;
BEGIN
latch : BLOCK ( ck = '1' )
BEGIN
Lat <= GUARDED D;in
END BLOCK;
In both cases, the guard expression must depend only on
one signal if the description is to be processed by the
logic synthetizer (bop
+ scmap
).
The following operators are only supported: NOT
,
AND
, OR
, XOR
, NOR
,
NAND
, &
, =
, /=
.
They can be applied on all types supported by the subset.
Other standard VHDL operators (+
, -
,
>
, <
, ...) have not been implemented
in the present release.
TIMING
A VHDL description can be used for:
- validation of a specification (behavioural)
- direct synthesis of hardware (behavioural)
- validation of a structural netlist
Detailed timing information is not available at design
time (cases 1 and 2).
For an extracted netlist (case 3) the detailed timing
analysis is performed by a specific tool: the static timing analyser
tas
.
Thus, timing specification is not supported by the
ALLIANCE VHDL subset. Simulation is performed in zero
delay mode.
ASSERT STATEMENT
Only two severity levels are supported in concurrent
assert statements:
WARNING
|
print a warning message if the assert condition is not satisfied.
|
ERROR
|
print an error message if the assert condition is not satisfied.
Then, stop the simulation.
|
Assert statements are ignored by the logic synthesis tool.
DON'T CARE
A special feature has been introduced in order to allow
"don't care" specification when the logic synthtizer is
targeted (Beware : this feature is incompatible with the
IEEE VHDL standard !!).
An output can be assigned to the value 'D' (don't care).
This is taken into account by the logic synthesis tool in
the optimization process. When the value of an output is
'D' the logic synthesis tool may turn it into a '1' or a
'0'.
A 'D' value is understood as a '0' by the logic simulator
(asimut
).
ARRAYS
Arrays other than BIT_VECTOR
, REG_VECTOR
,
MUX_VECTOR
and WOR_VECTOR
are not supported.
EXAMPLES
Here is the description of an adder with an accumulator register.
ENTITY add_accu IS
PORT (
clk : IN BIT;
command : IN BIT;
data_in : IN BIT_VECTOR ( 31 DOWNTO 0 );
data_out : OUT BIT_VECTOR ( 31 DOWNTO 0 );
cry_out : OUT BIT;
vdd : IN BIT;
vss : IN BIT
);
END add_accu;
ARCHITECTURE data_flow OF add_accu IS
SIGNAL eff_data : BIT_VECTOR ( 31 DOWNTO 0 ); -- effective operand
SIGNAL adder_out : BIT_VECTOR ( 31 DOWNTO 0 ); -- adder's result
SIGNAL adder_cry : BIT_VECTOR ( 32 DOWNTO 0 ); -- adder's carry
SIGNAL accum_reg : REG_VECTOR ( 31 DOWNTO 0 ) REGISTER; -- accumulator
CONSTANT initialize : BIT := '0';
CONSTANT accumulate : BIT := '1';
BEGIN
-- select the effective operand
WITH command SELECT
eff_data <= X"0000_0000" WHEN initialize,
accum_reg WHEN accumulate;
-- compute the result out of the adder
adder_out <= eff_data XOR data_in XOR adder_cry;
adder_cry ( 0 ) <= '0';
adder_cry ( 32 DOWNTO 1 ) <= ( eff_data AND adder_cry ( 31 DOWNTO 0 ) ) OR
( data_in AND adder_cry ( 31 DOWNTO 0 ) ) OR
( aff_data AND data_in );
-- write the result into the register on the falling edge of clk
write : BLOCK ( clk = '0' AND NOT clk'STABLE )
BEGIN
accum_reg <= GUARDED adder_out;
END BLOCK;
-- assign outputs
cry_out <= adder_cry ( 32 );
data_out <= accum_reg;
-- check power supply
ASSERT ( vdd = '1' AND vss = '0' )
REPORT "power supply is missing" SEVERITY ERROR;
END;
BUG REPORT
This tool is under development at the ASIM/LIP6/UPMC laboratory, cao-vlsi research team.
We need your feedbak to improve documentation and tools.
If you find bugs, please fill-in the form at
http://asim.lip6.fr/alliance/support/bug-report/
Thanks for doing this.
Laboratoire
d'Informatique de Paris 6
Université Pierre et Marie Curie - CNRS
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Alliance Web Site © 1997, 2002 ASIM/LIP6/UPMC,
page maintained by Czo [Olivier Sirol]
, last updated on 16 January 2001.