Hi, Dear Hassan Ahmadi, would you mind please to send your request on the Alliance support mailing : alliance-support@asim.lip6.fr (Much more people can try to answer you) This example is not complete, so i can do nothing to help you. I don't know what the signal state is, i don't know how the signal state can change its value etc ... This example seems to describe the generation function of a Finite State Machine with output register (sync). I advice you to have a look on the manual pages of syf(1) (FSM synthesizer) and fsm(5). (fsm file format). May be you can see also the tutorial attached to this mail. (It Works with the Alliance release 4) On Thu, Feb 10, 2000 at 10:01:31AM +0100, hassan Ahmadi wrote: > Dear sir > please help me how i kann translate the example in > alliance sudset: > > her the EXAMPLE: > > process (clk, reset) > begin > if reset='1' then > sync <= '0'; > elsif clk'event and clk='1' then > case state is > when RESET1 => sync <= '0'; > when RESET2 => sync <= '0'; > when FETCH => sync <= '0'; > when START_IRQ => sync <= '0'; > when START_NMI => sync <= '0'; > when RUN => > if done=MC_DONE then > if nmi_event='1' then > sync <= '0'; > elsif i_flag='0' and irq_reg='1' then > sync <= '0'; > else > sync <= '1'; > end if; > end if; > when others => sync <= '0'; > end case; > end if; > end process; > > > thank you very much for your help > __________________________________________________________________ > Do You Yahoo!? > Gesendet von Yahoo! Mail - http://mail.yahoo.de > Yahoo! Auktionen - gleich ausprobieren - http://auktionen.yahoo.de -- (_) ___ Ludovic JACOMME _ _ ( ) ( ) ( ) ( 6 ) Laboratoire LIP6, Equipe ASIM ( ) (_) ( _ ) Couloir 55-65, 2eme etage, ( )___ ( ) Universite P. et M. Curie (P6) (_____) (_) 4 place Jussieu, 75252 Paris Cedex 05 Tel: (33) 01.44.27.54.15 Fax: (33) 01.44.27.72.80 ICQ: 62526530 e-mail: Ludovic.Jacomme@asim.lip6.fr