I've been experimenting with the standard cell router, scr, compiled from the 3.2c source. First, I tried routing the netlist of 3 nand gates from the al(5) manpage, using a command line like "scr -c chan -r 1 -p -r test_nand.al" I get reasonable output, except that the first connection in the source netlist is consistently not routed to the edge of the output cell. (.al file attached below - connector "a" isn't routed out.) What I'm really trying to do is assemble standard cells that I've layed out in magic to produce blocks of magic layout that can be assembled into a full chip. To this end, I've put together ap2mag and mag2ap perl scripts that convert connectors and metal wiring between ap and magic format. While magic and ap have quite difference notions of transistors, wiring translates fairly directly. I've successfully transformed a logic cell from .mag to .ap, routed a tiny netlist using scr that uses these cells, and transformed the resulting channel, row, and top cells back into magic. While experimenting with this flow, the follwing questions come up: scr output: - scr still neglects to route the first port in the input netlist. - How are the sizes of the metal power wires that scr writes to the top-level output cell determined? In particular, the width of the horizontal metal1 wires doesn't adjust to match the power connectors on the logic cells. - How does s2r pick the size of the signal wires in the channel cells that it writes? The metal2 wires seem to be fixed at 2 alliance-lambdas, the m1 wires at 1 lambda. Can these be changed? - scr folds netnames to lowercase. Can this be stopped? - what do the various subcell transforms in the I lines of .ap files mean? The ap(5) man page leaves this out. NOSYM appears to be a simple translation, but what about ROT_P, SYMXY, ROT_M, SYM_X, SY_RM, SYM_Y, SY_RP? scr input: - With some experimentation, I figured out a way to place the ports on subcells (connectors on top and bottom) so I get reasonable output. Is there a guide to cell library layout that documents the requirements for building cells? - Is it possible to relax the pitch requirement for ports on input cells? (I don't mind hacking the code) - Why does scr need the logical description (.al file) of the cells referenced by the input netlist? Thanks for any pointers. -- Steve Tell | tell@cs.unc.edu | http://www.cs.unc.edu/~tell | KF4ZPF Research Associate, Microelectronic Systems Laboratory Computer Science Department, Computer Science Department, UNC@Chapel Hill. W:919-962-1845 test_nand.al file: V ALLIANCE : 4 H test_nand,L,13/ 8/93 C a,IN,EXTERNAL,0 C b,IN,EXTERNAL,1 C c,IN,EXTERNAL,2 C d,IN,EXTERNAL,3 C s,OUT,EXTERNAL,4 C vdd,IN,EXTERNAL,5 C vss,IN,EXTERNAL,6 I na2_y,i1 C i0,IN,INTERNAL,1 C i1,IN,INTERNAL,0 C f,OUT,INTERNAL,7 C vdd,IN,INTERNAL,5 C vss,IN,INTERNAL,6 I na2_y,i2 C i0,IN,INTERNAL,3 C i1,IN,INTERNAL,2 C f,OUT,INTERNAL,8 C vdd,IN,INTERNAL,5 C vss,IN,INTERNAL,6 I na2_y,i3 C i0,IN,INTERNAL,7 C i1,IN,INTERNAL,8 C f,OUT,INTERNAL,4 C vdd,IN,INTERNAL,5 C vss,IN,INTERNAL,6 S 8,INTERNAL,32.4,y S 7,INTERNAL,36.4,x S 6,EXTERNAL,22,vss S 5,EXTERNAL,22,vdd S 4,EXTERNAL,10.4,s S 3,EXTERNAL,10.4,d S 2,EXTERNAL,10.4,c S 1,EXTERNAL,10.4,b S 0,EXTERNAL,10.4,a EOF