alliance-support '02
Re: ActiveHDL


Ludovic JACOMME (Ludovic.JACOMME@asim.lip6.fr)
Fri, 1 Mar 2002 09:21:59 +0100

Hi David, On Thu, Feb 28, 2002 at 04:45:02PM -0800, David Elmore wrote: > Ludovic, > Thank you very much for the package you sent previously. > We have included the package with our design files. There seems to be > one thing lacking, however. Is there a package that defines logical > operations between BIT_VECTORS and REG_VECTORS? If you can point me to > one, I would be in your debt. Thank you. As far as i known, unfortunately there is no such a package. All designs i've seen where described using convert function ex: s <= bit_vector(reg_vector_signal) xor bit_vector_signal; You can also try to use VASY tool. It translates a .vbe file to a .vhd file (with std_logic_1164 types), and .vhd file to a .vbe file. But the resulting translated file is not very readable ;) > > > -- > David Elmore > The MicroDisplay Corporation > 3055 Research Drive > San Pablo, Calif. 94806 > Phone: (510)-243-9515 x115 > FAX: (510)-243-9522 > Regards, Ludovic. (_) ___ Ludovic JACOMME _ _ ( ) ( ) ( ) ( 6 ) Laboratoire LIP6, Equipe ASIM ( ) (_) ( _ ) Couloir 65-66, 4eme etage Porte 405, ( )___ ( ) Universite P. et M. Curie (P6) (_____) (_) 4 place Jussieu, 75252 Paris Cedex 05 Tel: (33) 01.44.27.27.06 01.44.27.54.15 Fax: (33) 01.44.27.72.80 ICQ: 62526530 mailto: Ludovic.Jacomme@asim.lip6.fr http: //www-asim.lip6.fr/~ludo

 



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