One of our main goal is process independence. The process independence relies on a symbolic layout approach and a fully automatic process mapping from a silicon supplier to another. The existing portable libraries are designed for standard CMOS process with one poly and two metals. New high performance library is being designed. Besides providing VLSI CAD tools with their own portable cells libraries, we are also aware of industry standard CAD systems, this is why we want to provide design kits for Cadence and Synopsys. Some of these kits are still under develloppement, so check ftp://asim.lip6.fr/pub/alliance/design-kits/ often for avaibility.

 

 



Alliance Web Site © 1997, 2002 ASIM/LIP6/UPMC, page maintained by Czo [Olivier Sirol] , last updated on 26 January 2001.