alliance-support '2000
Re: Simulating multiple chips


Ludovic JACOMME (Ludovic.JACOMME@asim.lip6.fr)
Mon, 21 Feb 2000 18:32:20 +0100

Hi, You have to describe all blocks of your design in a separate file (where the file name is the name of the block/model, see vbe(5)), and to describe the interconnection of those blocks in a structural description using vst format (see man page vst(5) for details) On Fri, Feb 18, 2000 at 12:50:09PM -0500, Pierre Abbat wrote: > The system I'm designing will have other chips, such as counters and ROMs, as > well as the latch. Do I put them in separate entities in the same file, or in > different files? How do I connect them? > > phma Hope this help, regards, Ludo. (_) ___ Ludovic JACOMME _ _ ( ) ( ) ( ) ( 6 ) Laboratoire LIP6, Equipe ASIM ( ) (_) ( _ ) Couloir 55-65, 2eme etage, ( )___ ( ) Universite P. et M. Curie (P6) (_____) (_) 4 place Jussieu, 75252 Paris Cedex 05 Tel: (33) 01.44.27.54.15 Fax: (33) 01.44.27.72.80 ICQ: 62526530 mailto: Ludovic.Jacomme@asim.lip6.fr http: //asim.lip6.fr/~ludo

 



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