Hi, attached to this mail you will fin the vst description of a (5,3) counter as well as the .ap file produced by the router using the command scr -p -r -l 1 <cell name>. As you will see the channel routing (using sclib) is completely wrong. However this is only a minor bug because in some cases SCR does nor perfor the channel routing and i have had to do it by hand!!! This is only a test file; my design is much more complex and uses CPL differential logic that I have created by myself using GRAAL. The design is a bitsliced multiplier, where a row i produces the bit of weight 2^i of the result. The multiplier is described bitslice by bitslice and the routin is done separately for each bitslice forcing the layout to occupy one row using scr -p -r -l 1 <slice name>; however for some slice the standard cell are only placed but not routed. I cannot picture myself the cause of all this, maybe a wrongly set environment variable...... Please let me know. Best regards, --Gianluca
V ALLIANCE : 4 H std53count,P,29/08/2000,100 A 0,0,39500,7300 C 20550,0,300,vss,0,SOUTH,ALU2 C 19850,0,300,vdd,0,SOUTH,ALU2 C 20550,7300,300,vss,3,NORTH,ALU2 C 19850,7300,300,vdd,3,NORTH,ALU2 C 39500,3100,600,vss,2,EAST,ALU1 C 39500,6700,600,vdd,2,EAST,ALU1 C 0,3100,600,vss,1,WEST,ALU1 C 0,6700,600,vdd,1,WEST,ALU1 C 6300,0,200,i4,0,SOUTH,ALU2 C 5700,0,200,i3,0,SOUTH,ALU2 C 8100,0,200,i2,0,SOUTH,ALU2 C 29000,0,200,i1,0,SOUTH,ALU2 C 28400,0,200,i0,0,SOUTH,ALU2 C 37400,0,200,o2,0,SOUTH,ALU2 C 35600,0,200,o1,0,SOUTH,ALU2 C 18900,0,200,o0,0,SOUTH,ALU2 S 1500,2400,5500,2400,200,i3,RIGHT,ALU1 S 3000,1900,6000,1900,200,i4,RIGHT,ALU1 S 4500,1400,7000,1400,200,t_0,RIGHT,ALU1 S 7000,2400,9500,2400,200,t_0,RIGHT,ALU1 S 7500,1900,12000,1900,200,t_3,RIGHT,ALU1 S 8000,1400,10000,1400,200,i2,RIGHT,ALU1 S 10000,2400,11500,2400,200,i2,RIGHT,ALU1 S 12000,2400,14000,2400,200,t_3,RIGHT,ALU1 S 12500,1900,29500,1900,200,t_1,RIGHT,ALU1 S 13500,1400,14500,1400,200,t_5,RIGHT,ALU1 S 14500,2400,39000,2400,200,t_5,RIGHT,ALU1 S 15500,1400,30500,1400,200,t_2,RIGHT,ALU1 S 24000,900,28000,900,200,i0,RIGHT,ALU1 S 26000,400,29000,400,200,i1,RIGHT,ALU1 S 30000,1900,36500,1900,200,t_4,RIGHT,ALU1 S 32500,1400,37500,1400,200,t_6,RIGHT,ALU1 S 37500,1900,38000,1900,200,t_6,RIGHT,ALU1 S 1500,2400,1500,5300,200,i3,UP,ALU2 S 3000,1900,3000,5300,200,i4,UP,ALU2 S 4500,1400,4500,5300,200,t_0,UP,ALU2 S 5500,0,5500,5300,200,i3,UP,ALU2 S 6000,0,6000,5300,200,i4,UP,ALU2 S 6500,1400,6500,5300,200,t_0,UP,ALU2 S 7000,1400,7000,2400,200,t_0,UP,ALU2 S 7500,1900,7500,5300,200,t_3,UP,ALU2 S 8000,0,8000,5300,200,i2,UP,ALU2 S 9500,2400,9500,5300,200,t_0,UP,ALU2 S 10000,1400,10000,2400,200,i2,UP,ALU2 S 11500,2400,11500,5300,200,i2,UP,ALU2 S 12000,1900,12000,2400,200,t_3,UP,ALU2 S 12500,1900,12500,5300,200,t_1,UP,ALU2 S 13500,1400,13500,5300,200,t_5,UP,ALU2 S 14000,2400,14000,5300,200,t_3,UP,ALU2 S 14500,1400,14500,2400,200,t_5,UP,ALU2 S 15500,1400,15500,5300,200,t_2,UP,ALU2 S 17500,1900,17500,5300,200,t_1,UP,ALU2 S 18500,0,18500,5300,200,o0,UP,ALU2 S 24000,900,24000,5300,200,i0,UP,ALU2 S 26000,400,26000,5300,200,i1,UP,ALU2 S 27000,1400,27000,5300,200,t_2,UP,ALU2 S 28000,0,28000,5300,200,i0,UP,ALU2 S 29000,0,29000,5300,200,i1,UP,ALU2 S 29500,1900,29500,5300,200,t_1,UP,ALU2 S 30000,1900,30000,5300,200,t_4,UP,ALU2 S 30500,1400,30500,5300,200,t_2,UP,ALU2 S 32500,1400,32500,5300,200,t_6,UP,ALU2 S 34000,2400,34000,5300,200,t_5,UP,ALU2 S 35500,0,35500,5300,200,o1,UP,ALU2 S 36000,1400,36000,5300,200,t_6,UP,ALU2 S 36500,1900,36500,5300,200,t_4,UP,ALU2 S 37000,0,37000,5300,200,o2,UP,ALU2 S 37500,1400,37500,1900,200,t_6,UP,ALU2 S 38000,1900,38000,5300,200,t_6,UP,ALU2 S 39000,2400,39000,5300,200,t_5,UP,ALU2 S 20550,0,20550,7300,300,vss,UP,ALU2 S 19850,0,19850,7300,300,vdd,UP,ALU2 S 20500,3100,20600,3100,600,*,RIGHT,ALU2 S 20500,3100,20600,3100,600,*,RIGHT,ALU1 S 20550,2900,20550,3300,300,*,UP,ALU2 S 20550,2900,20550,3300,300,*,UP,ALU1 S 19800,6700,19900,6700,600,*,RIGHT,ALU2 S 19800,6700,19900,6700,600,*,RIGHT,ALU1 S 19850,6500,19850,6900,300,*,UP,ALU2 S 19850,6500,19850,6900,300,*,UP,ALU1 S 19200,6700,21200,6700,600,vdd,RIGHT,ALU1 S 19200,3100,21200,3100,600,vss,RIGHT,ALU1 I 0,2800,xr2_y,xor1,NOSYM I 4800,2800,nmx2_y,aoi1,NOSYM I 8400,2800,xr2_y,xor2,NOSYM I 13200,2800,n1_y,inv1,NOSYM I 14400,2800,xr2_y,xor4,NOSYM I 21200,2800,rowend_x0,feed0,NOSYM I 21700,2800,rowend_x0,feed1,NOSYM I 22200,2800,rowend_x0,feed2,NOSYM I 22700,2800,xr2_y,xor3,NOSYM I 27500,2800,nmx2_y,aoi2,NOSYM I 31100,2800,xr2_y,xor5,NOSYM I 35900,2800,n1_y,inv2,NOSYM I 37100,2800,a2_y,and1,NOSYM V 1500,2400,CONT_VIA V 3000,1900,CONT_VIA V 4500,1400,CONT_VIA V 5500,2400,CONT_VIA V 6000,1900,CONT_VIA V 6500,1400,CONT_VIA V 7000,2400,CONT_VIA V 7000,1400,CONT_VIA V 7500,1900,CONT_VIA V 8000,1400,CONT_VIA V 9500,2400,CONT_VIA V 10000,2400,CONT_VIA V 10000,1400,CONT_VIA V 11500,2400,CONT_VIA V 12000,2400,CONT_VIA V 12000,1900,CONT_VIA V 12500,1900,CONT_VIA V 13500,1400,CONT_VIA V 14000,2400,CONT_VIA V 14500,2400,CONT_VIA V 14500,1400,CONT_VIA V 15500,1400,CONT_VIA V 17500,1900,CONT_VIA V 24000,900,CONT_VIA V 26000,400,CONT_VIA V 27000,1400,CONT_VIA V 28000,900,CONT_VIA V 29000,400,CONT_VIA V 29500,1900,CONT_VIA V 30000,1900,CONT_VIA V 30500,1400,CONT_VIA V 32500,1400,CONT_VIA V 34000,2400,CONT_VIA V 36000,1400,CONT_VIA V 36500,1900,CONT_VIA V 37500,1900,CONT_VIA V 37500,1400,CONT_VIA V 38000,1900,CONT_VIA V 39000,2400,CONT_VIA V 20550,3100,CONT_VIA V 19850,6700,CONT_VIA EOF
-- VHDL structural description generated from `sc53` -- date : Thu Aug 17 11:28:58 2000 -- Entity Declaration ENTITY sc53 IS PORT ( i4 : in BIT; -- i4 i3 : in BIT; -- i3 i2 : in BIT; -- i2 i1 : in BIT; -- i1 i0 : in BIT; -- i0 o2 : out BIT; -- o2 o1 : out BIT; -- o1 o0 : out BIT; -- o0 vdd : in BIT; -- vdd vss : in BIT -- vss ); END sc53; -- Architecture Declaration ARCHITECTURE VST OF sc53 IS COMPONENT xr2_y port ( i0 : in BIT; -- i0 i1 : in BIT; -- i1 t : out BIT; -- t vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT a2_y port ( i0 : in BIT; -- i0 i1 : in BIT; -- i1 t : out BIT; -- t vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT nmx2_y port ( j0 : in BIT; -- j0 j1 : in BIT; -- j1 i0 : in BIT; -- i0 i1 : in BIT; -- i1 f : out BIT; -- f vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT n1_y port ( i : in BIT; -- i1 f : out BIT; -- f vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; SIGNAL t_0 : BIT; -- t 0 SIGNAL t_1 : BIT; -- t 1 SIGNAL t_2 : BIT; -- t 2 SIGNAL t_3 : BIT; -- t 3 SIGNAL t_4 : BIT; -- t 4 SIGNAL t_5 : BIT; -- t 3 SIGNAL t_6 : BIT; -- t 4 SIGNAL t_7 : BIT; -- t 3 SIGNAL t_8 : BIT; -- t 4 BEGIN -- bit 0 xor1 : xr2_y PORT MAP (i4,i3,t_0,vdd,vss); xor2 : xr2_y PORT MAP (i2,t_0,t_1,vdd,vss); xor3 : xr2_y PORT MAP (i1,i0,t_2,vdd,vss); xor4 : xr2_y PORT MAP (t_1,t_2,o0,vdd,vss); -- bit 1 aoi1 : nmx2_y PORT MAP (i4,i3,t_0,i2,t_3,vdd,vss); aoi2 : nmx2_y PORT MAP (i1,i0,t_1,t_2,t_4,vdd,vss); inv1 : n1_y PORT MAP (t_3,t_5,vdd,vss); inv2 : n1_y PORT MAP (t_4,t_6,vdd,vss); xor5 : xr2_y PORT MAP (t_5,t_6,o1,vdd,vss); --bit 2 and1 : a2_y PORT MAP (t_5,t_6,o2,vdd,vss); end VST;