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Name

ttv - The timing analyzer tas report : `general perfmodule' format.

Origin

This software belongs to the ALLIANCE CAD system from the CAO-VLSI team at ASIM/LIP6/UPMC laboratory.
LIP6/ASIM
University P. et M. Curie 4, place Jussieu 75252 PARIS Cedex 05 FRANCE
Fax : {33/0} 1.44.27.62.86
E-mail support : alliance-support@asim.lip6.fr

Description

The timing analyzer tas reports its results in a file, named `perfmodule'. There are two kind of perfmodules: the `intermediate' (or `detailed") and the `general'. The first one has a htv extension and is obtained if the -t option is used. It contains gate delays between two signals. The second one has the ttv extension and contains all critical paths between two reference points. The perfmodule has several articles.

Terminals
Terminals are reported on the X article.

X direction name capacitance ;

The `terminal' direction can be:

I
for an input terminal
T
for a transceiver terminal
B
for a bidirectional terminal
O
for an output terminal
Z
for a high-impedance terminal
U
for an unknown direction
Latches
Latches are reported on the L article.

L name ( cmd1 cmd2 ... ) ;

A latch may have several commands. All of them belong to the L article.

Precharged signals Precharged signals are reported on the P article.

P name ;

Transitions
Transitions between signals are reported to the T article.

T type begin end ( (control (input_commutation output_commutation delay resistance slope))) ;

Each `transition' has one of the following type:

E
if the path output is a precharged signal and the transition concerns an evaluation phase.
P
if the path output is a precharged signal and the transition concerns an precharged phase.
X
if the output is not a precharged signal.

Each `commutation' has one of the following type:

U
for a rising edge.
D
for a falling edge.
Z
for a commutation when the output is a precharged signal.

If the end of path is a register, the `control' field indicates which signal controls the transition. And if the end of path is a terminal, in each transition, the output resistance and the output slope will be reported. This allows a hierarchical analysis. In the other case, only the delay appears in the transition line.

See Also

tas(1) ,dtv(5)

Bug Report

This tool is under development at the ASIM/LIP6/UPMC laboratory, cao-vlsi research team.
We need your feedbak to improve documentation and tools. If you find bugs, please fill-in the form at http://asim.lip6.fr/alliance/support/bug-report/ Thanks for doing this.


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