fpmap - fpga mapper of a logic level behavioural description (VHDL data flow)
This software belongs to the ALLIANCE CAD system from the CAO-VLSI team at
ASIM/LIP6/UPMC laboratory.
LIP6/ASIM
University P. et M. Curie
4, place Jussieu
75252 PARIS Cedex 05
FRANCE
Fax : {33/0} 1.44.27.62.86
E-mail support : alliance-support@asim.lip6.fr
fpmap -Tarchi [options] data_flow_file output_file [parameter_file]
Input description
The logic level behavioural description (.vbe file) uses the same VHDL
subset as the logic simulator asimut, the FSM synthesizer syf, the functional
abstractor yagle and the formal prover proof (for further information
about the subset of VHDL, see the vbe manual).
A special feature has been introduced in the VHDL subset in order to allow
the don't care description for external outputs and internal registers : A
bit signal can take the `d' value. This value is interpreted as a `0' by
the logic simulator asimut. Don't Cares are automatically generated by
syf in the resulting `.vbe' file.
For the register signal, only one signal can appear in a guarded expression.
Since most of the fpga devices have a separate write enable input on
their registers, it can be used in the description using a when .. else
statement (reg <= input when write_enable else reg;).
Parameter file `.lax'
The parameter file is common with other logic synthesis tools and is used
for driving the synthesis process. See lax(5)
manual for more detail.
The following environment variables have to be set before using fpmap :
MBK_WORK_LIB gives the path of the directory of both input and output files (behavioural, structural and parameters description).
MBK_OUT_LO gives the output format of the structural description.
-O[0-5] defines the level of optimization. O0 means no optimisation at all, O5 is the highest degree of optimization. If the level of optimization is set both in the .lax parameter file and on the command line, the latter is keeped.
You can call fpmap as follows :
fpmap -TX4000 -afn sequncer
proof(1) , yagle(1) , asimut(1) , vhdl(5) .
This tool is under development at the ASIM/LIP6/UPMC laboratory, cao-vlsi
research team.
We need your feedbak to improve documentation and tools.
If you find bugs, please fill-in the form at
http://asim.lip6.fr/alliance/support/bug-report/
Thanks for doing this.