rsa - call the Recurrence Solver Adder generator
This software belongs to the ALLIANCE CAD system from the CAO-VLSI team at
ASIM/LIP6/UPMC laboratory.
LIP6/ASIM
University P. et M. Curie
4, place Jussieu
75252 PARIS Cedex 05
FRANCE
Fax : {33/0} 1.44.27.62.86
E-mail support : alliance-support@asim.lip6.fr
#include gga300.h"
char *rsa(n, cin, cout, overn, not,
csa, sub, addsub,
over, deci, stretch, stretch2,
msb0, virtual,
layout, icon, vhdl, patterns, datasheet,
physicalbox-logicalbox-perf,
name)
int n, cin, cout, overn, not,
csa, sub, addsub,
over, deci, stretch, stretch2,
msb0, virtual,
layout, icon, vhdl, patterns, datasheet,
physicalbox-logicalbox-perf,
char *name;
cout The generated adder will contain all the intermediates carry, accessible in Metal2 Layer, with the multi-access possibilities.
overn The generated adder will contain the previous carry output over in Metal1 layer on the North side. This signal could be used to calculate an overflow flag = over^cout.
a-b. If the option -cin is present, then the block calculates a+not(b)+cin .
addsub The block obtained is a adder/subtractor. If the input terminal is set to 5V then it is a subtractor. If the option -cin is present, then the block performs a+xor(b,sub)+cin.
over -deci -stretch -stretch2
Bull Options.
msb0 Default is index 0 for the least significant bit. When -msb0 is present the the most significant bit is indexed with 0.
virtual
Default blocks contain fixed terminals. Virtual terminals can be
obtained using this option. This way, dpr(1)
routershouldoptimizedtheresultantrouteddata-path.
layout The generated view asked is a layout view. The different formats are given by mbk(1) documentation, using MBK_OUT_PH(1) environment variable.
icon Icon view for schematic capture. The possible output formats are specified setting the ICON_OUT (1) environement variable.
vhdl The generated view asked is a data-flow behavioural view. The description of the VHDL used is gived by vhdl(5) .
patterns
Some test vectors are proposed to validate the generated block. The
format used is the pat(5)
one accepted by the VHDL simulator
asimut(1)
.
datasheet
Principals process dependent informations are proposed to estimate
the adder performances. It is the default view if none is specified.
physicalbox
The generated view asked is a interface view. The different formats
are given by mbk(1)
documentation, using MBK_OUT_PH(1)
environment
variable.
logicalbox
The generated view asked is an interface netlist view. The different
formats are given by mbk(1)
documentation, using MBK_OUT_LO(1)
environment variable.
MBK_IN_PH(1) , vhdl(5) , pat(5) , rsa(1) , rfg(1) , bsg(1) , grog(1) ,
This tool is under development at the ASIM/LIP6/UPMC laboratory, cao-vlsi
research team.
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If you find bugs, please fill-in the form at
http://asim.lip6.fr/alliance/support/bug-report/
Thanks for doing this.