Hi, I have just downloaded the new version of the SCR tool that you give and used it successly to place and route 'core.vst' as a result of using 'genlip' for core.c, like it scr -sclib -p -r core Unfortunately there was a error after I extracted core.ap using 'lynx command' lynx -v core core like this : rpr:rprparse.1945 error missing value line 234 in technological file /home/cad/alliance/share/etc/cmos_7.rds Because that I can not go on to real layout translation. I dont know the new vesion SCR is wrong or not. If I use the old version of the SCR tool the routing run continously, never stop, for addaccu and AMD 2901 tutorials with command scr -p -r core for input core.vst and scr -p -r heart for input heart.vst (AMD 2901). Please, I hope you can give me any sugestion , mainly aboutthat error. The full result is : [[marta@ic-02 ~/addaccu]# setenv MBK_IN_LO vst [[marta@ic-02 ~/addaccu]# setenv MBK_IN_PH ap [[marta@ic-02 ~/addaccu]#setenv MBK_OUT_PH ap [[marta@ic-02 ~/addaccu]# setenv MBK_CATA_LIB $TOP/share/cells/sclib [[marta@ic-02 ~/addaccu]# scr -sclib -p -r core @@@@ @ @@@@ @ @@@@@@@ @ @@ @@ @@ @@ @@ @@ @ @@ @ @@ @@ @@@ @@ @ @@ @@ @@@@ @@ @@ @@ @@@@ @@ @@@@@ @@@ @@ @@ @@ @ @@ @@ @@ @@ @@ @@ @@ @ @@ @@ @@@ @ @@ @@ @@ @@ @ @@@@ @@@@ @@@@@ @@@ Standard Cell router Alliance CAD System 4.0.7, scr 5.3 Copyright (c) 1991-2000, ASIM/LIP6/UPMC E-mail support: alliance-support@asim.lip6.fr Loading logical view : core Placing logical view : core Loading SCP data base ... Original width : 400 Generating initial placement ... 25 cells 37 nets in 3 rows Placement in process of treatment : 100% 52% saved in 0.4 s Saving placement 100% Checking consistency between logical and physical views Loading SCR data base ... Deleting MBK data base ... Global routing ... Channel routing ... |_____Routing Channel : scr_p2 |_____Routing Channel : scr_p4 |_____Routing Channel : scr_p6 |_____Routing Channel : scr_p8 Making vertical power and ground wires Saving layout : core [[marta@ic-02 ~/addaccu]# setenv MBK_IN_PH ap [[marta@ic-02 ~/addaccu]# setenv MBK_OUT_LO al [[marta@ic-02 ~/addaccu]# setenv RDS_TECHNO_NAME $TOP/share/etc/cmos_7.rds [[marta@ic-02 ~/addaccu]# setenv MBK_CATA_LIB $TOP/share/cells/sclib:$TOP/share/c ells/padlib [[marta@ic-02 ~/addaccu]# lynx -v core core @@@@@@ @@ @@ @@ @@@@@ @@@ @@@ @@@ @@@@ @@@ @@ @@ @ @@@ @ @@ @ @@ @@ @ @@ @@ @@ @ @@ @@ @ @@ @@ @@@ @@ @@ @ @@ @@ @@@ @@ @ @@@ @@ @@ @ @@ @@ @ @@ @@ @@ @ @@ @@@@@@@@@@ @@ @ @@@@ @@@@ @@@ @@@@ @@ @ @@@ Netlist extractor Alliance CAD System 4.0.6, lynx 1.20 Copyright (c) 1998-2000, ASIM/LIP6/UPMC Author(s): Ludovic Jacomme and Gregoire Avot Contributor(s): Picault Stephane E-mail support: alliance-support@asim.lip6.fr ---> Parse technological file rpr:rprparse.1945 error missing value line 234 in technological file /home/cad/alliance/share/etc/cmos_7.rds MARTADINATA