Pei-Hsiuan Chou wrote: To whom it may concern: I am an EE major graduate student at University of Alabama at Birmingham. Currently I am evaluating Alliance for upcoming VLSI design course. I tried to use Alliance to generate a physical layout from VHDL behavioral description which is files with .vbe for Alliance. After reading the overview of Alliance and the addaccu tutorial, the answer is still not clear to me. Would you please help me on this question. If it's possible to generate a chip layout by using Alliance and a VHDL behavioral description file. If the answer is "yes", which Alliance tools and what procedures I should use. Yes, you'll have to use *bop* & *scmap* (also *syf* if you have FSM) bop optimizes the vbe file scmap maps a vbe to a vst -- Sincerely, Olivier. ==================================================================== Olivier SIROL Alliance Team ASIM/LIP6/UPMC Coul. 55-65, 2e etg, Bur. 213 75252 Paris Cedex 05 mailto:Olivier.Sirol@lip6.fr Tel: (33/0) 1.44.27.74.78 http://asim.lip6.fr/~czo/ Fax: (33/0) 1.44.27.72.80