Table of Contents

Name

bgd - register file generator

Synopsis

bgd
bgd -h
bgd -deco crunch_name
bgd bits words busses
[ li ] [ lo ] [ id ] [ lp ] [ wel|weh ] [ dsh|ish ] [ hc ] ro|rs|ds|ba
[ name=name_prefix ]
layout|outline|vhdl|data|netlist
[ layout ] [ outline ] [ vhdl ] [ data ] [ netlist ]

Origin

This software belongs to the ALLIANCE CAD system from the CAO-VLSI team at ASIM/LIP6/UPMC laboratory.
LIP6/ASIM
University P. et M. Curie 4, place Jussieu 75252 PARIS Cedex 05 FRANCE
Fax : {33/0} 1.44.27.62.86
E-mail support : alliance-support@asim.lip6.fr

Availability

This command is available with MBK/GENLIB software installation option.

Description

The first form is a on line help.

The second is a long on line help.

In the third form, bgd decrunch prefix name who have been generated by himself.

In the last form, bgd generates differents views of a register file and offers a very large range of possible parameters. The generator respect the CAO-VLSI definition of a data-path. The slice is fixed at 60 lambdas, allows multi-acces connectors, could be used with the data-path router dpr(1) .

The generator needs a library cells to well compute. The MBK_CATA_LIB environment variable should contain the path to the library, /labo/cells/bgd.

Parameters and Options

-h
Help (long form).
-deco crunch_name
Name decrunch function. crunch_name : XXYYYYY.
XX
: prefix of Bank Generator bloks name. YYYYY : 5 charaters for parameters incoding.
bits
Word size. The range is from 2 to 64, the value must be even.

words Number of registers. The range is from 2 to 256, the value must be even.

busses Number of read busses : 1 or 2. Generated register file has one write address bus and one or two read address busses.

li
Adds an input latch
lo
Adds output latches. One latch for each output bus.
id
Inverts data polarity between input bus and output busses.
lp
Reduces consumption but increases read time. This option is only available for register file which have more than 16 registers.
wel
Adds a write enable signal. The signal is actif low.
weh
Adds a write enable signal. The signal is actif high.
dsh
Adds a bypass to each output bus. Data polarity between bypass inputs and outputs is preserved.
ish
Adds a bypass to each output bus. Data polarity between bypass inputs and outputs is inverted.
ro
Generates a block without address decoders, with an optimized width.
rs
Generates a block without address decoders, that could be abuted with a decoders block.
ds
Generates a block that contains only the address decoders. This block has the same size and the same connectors interface as the block generated with the rs option.
ba
Generates a complete register file with address decoders.

name=name_prefix
name_prefix indicate the user name prefix for all files generated. If no name is given, the default files prefix is : XXYYYYY Where XX is ro | rs | ds | ba and YYYYY is an encode of the parameter values ensuring an unique name.

layout To obtain a layout view. The different formats are given by mbk(1) documentation.

outline
To obtain a outline view.

vhdl
To obtain a VHDL data-flow behavioural description view.
data
To obtain a data sheet.

netlist
To obtain a netlist view. This view contains only the logical block interface. The different formats are given by mbk(1) documentation.

Examples

bgd 24 16 2 rs name=my_reg outline
Produces the outline view of 16 registers of 24 bits with 2 read busses. The generated file name is my_reg.edif".

bgd 16 32 1 wel ba name=test layout vhdl Produces the layout and vhdl views of a 32 registers of 16 bits complete register file with 1 read bus and a write enable input active at low level. The prefix name of all generated files is test".

Signal Names

Each signal name is predefined and could not be modified by the user. Index 0 is the most significant bit and N represent the number of bits. M represent the size of address busses, this size depend on number of registers. Signal names are :

ad_w[0]-ad_w[M-1]
Write address

we
Write enable signal

ad_r_a[0]-ad_r_a[M-1]
First read address

ad_r_b[0]-ad_r_b[M-1]
Second read address

c_s_a First bypass control signal

c_s_b Second bypass control signal

ck_m
Master clock signal
ck_s
Slave clock signal

in_a[0]-in_a[N-1]
Data input

i_s_a[0]-i_s_a[N-1]
First bypass data input

i_s_b[0]-i_s_b[N-1]
Second bypass data input

out_a[0]-out_a[N-1]
Fisrt data output

out_b[0]-out_b[N-1]
Second data output

vdd, vss
Power supplies

Topology

The complete register file dimension are approximately : width = words * 34 lambdas.
height = (bits + 3 * busses + 6) * 60 lambdas.

See Also

mbk(1) , dpr(1) ,

Bug Report

This tool is under development at the ASIM/LIP6/UPMC laboratory, cao-vlsi research team.
We need your feedbak to improve documentation and tools. If you find bugs, please fill-in the form at http://asim.lip6.fr/alliance/support/bug-report/ Thanks for doing this.


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