alliance-support '1998
alliance beh -> struct; how to use scmap?


Hans van der Linden (linden@nand.et.tudelft.nl)
Wed, 11 Mar 1998 15:34:39 GMT

Hello, I am trying to see if I can use the alliance CAD framework. I worked my way through the addaccu and amd2901 tutorials (I needed to correct quite a lot of mistakes in the instructions in these tutorials before things worked out as they should...). Then it became clear to me that in both examples (of the tutorials) in fact the synthesis step between behavioural and structural level was missing, and the structure was already there at the start... Looking further in the man pages etc., I found the mappers such as scmap, and apparanetly they are what I was looking for, however, I tried to apply scmap to the addaccu behavioral description, only to get a core dump.....I will attach the scmap output so you can see if I did anything wrong. Please inform me what I am doing wrong, so I can get the scmap tools etc to run, and if possible please provide me with, or point me to, an example, such as the tutorials, or smaller, wherein the synthesis steps between behavioral and structural level are made clear. regards, hvdl @ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @ @@ @@ @@ @@ @@ @@ @@ @@@ @ @@ @@ @@ @@ @@ @@ @@@ @@@ @@ @ @@@@ @@@@ @@@@ @@@ @@@ @@@@ @@ @@ @@@ @@ @@@@ Mapping Standard Cells Alliance CAD System 3.2b, scmap 4.20 [1997/10/09] Copyright (c) 1990-1998, ASIM/LIP6/UPMC E-mail support: alliance-support@asim.lip6.fr ================================ Environment ================================ MBK_WORK_LIB = . MBK_CATA_LIB = /users/chimera/uj/linden/alliance/alliance/share/cells/sclib/:/users/chimera/uj/linden/alliance/alliance/share/cells/ring MBK_TARGET_LIB = /users/chimera/uj/linden/alliance/alliance/archi/Linux_elf/cells/sclib MBK_IN_LO = vst MBK_OUT_LO = vst ======================= Files, Options and Parameters ======================= VHDL file = addaccu.vbe output file = addaccuc4.vst Parameter file = default.lax Mode = Mapping standard cell Optimization mode = 50% area - 50% delay optimization Optimization level = 2 =============================================================================== Compiling 'addaccu' ... Running Standard Cell Mapping ============================= INITIAL COST ================================== Total number of literals = 194 Number of reduced literals = 57 Number of latches = 8 Maximum logical depth = 13 Maximum delay = 4.833 =============================================================================== Compiling library '/users/chimera/uj/linden/alliance/alliance/archi/Linux_elf/cells/sclib' Generating Expert System ... Cell 'cmx2_y' Unused Cell 'cry_y' Unused Cell 'sum_y' Unused Cell 'tie_y' Unused 162 rules generated ......Segmentation fault (core dumped) rerunnning it with the debugger around it gives the same, only ends in: Cell 'tie_y' Unused 162 rules generated ...... Program received signal SIGSEGV, Segmentation fault. 0x8084ad7 in free () Thanks in advance, best regards, hvdl /////////////////////////////////////////////////////////////////////////////// // Hans van der Linden Delft University of Technology // linden@fanout.et.tudelft.nl or J.Th.vdLinden@et.tudelft.nl

 



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