Dear Sir, I used Rage to generate a unidirecton port SRAM, then extracted its Spice netlist by Lynx (with -t option), but the netlist cannot match the layout in Cadence's Dracula LVS. I trace the problem is due to the cell "rage/dtio4_c". If I use "bidirection port" , then the layout will pass LVS check. I am not good at hacking layout vs. netlist. Do you have some comment of this case? If you can trace the LVS report, I can pass you all files. Thank you very much! ~harry