YAGLE - Functional abstraction of CMOS circuits
This software belongs to the ALLIANCE CAD system from the CAO-VLSI team at
ASIM/LIP6/UPMC laboratory.
LIP6/ASIM
University P. et M. Curie
4, place Jussieu
75252 PARIS Cedex 05
FRANCE
Fax : {33/0} 1.44.27.62.86
E-mail support : alliance-support@asim.lip6.fr
YAGLE [-v] [-d] [-b] [-z] [-nc] [-nh] [-p=n] [-fcl] [-i] [-os] [-t] file1 [file2]
YAGLE is a functional abstractor for CMOS digital circuits. It provides a
VHDL data flow description from a transistor level description of the circuit.
The transistor net-list can be flat or hierarchical. The VHDL subset
generated by YAGLE is supported by ASIMUT, BOP, SCMAP and PROOF.
Tri-state nodes of the circuit are expressed as VHDL Bus. Latches and registers
are expressed as VHDL Register signal. Yagle does not use a predefined
gate library except for latches and flip-flops. All styles or circuitry
are supported: dual-cmos, precharge, pass-transistor...
All power supplies and grounds signals must be connected to an external
connector.
In a first phase, YAGLE extracts the CMOS dual circuitry. In a second
phase, YAGLE builds the gate net-list for the remaining circuitry whilst
performing functional analysis in parallel, in order to prevent the fabrication
of false branches within a gate and to verify the behaviour of the
gate.
This functional analysis depends on the `n' parameter that defines the
maximum depth (in gates) of the analysis.
Options may be given in any order before or after the filename(s).
In addition the user can specify a behavioural description for the transistor netlist in the .vbe format (see man vbe) which is used to generate the global behavioural description of the circuit. This allows the functional abstraction of circuits containing analog blocks for example RAMs containing sense amplifiers.
Port name may be preceded by the character `~' which minds that it is the inverse of the port which has to be taken into account.
The user can also use this file to rename internal signals in the behavioural description in order to use the formal proof.
new_name will replace existing_name in the behavioural description file. It is possible to use the joker `*'. When the names contain the string gno", this string is replaced by the string latch_data (l2_y_gno_01 is replaced by l2_y_latch_data_01).
Beware that only one rule can be applied to a name, (the following rules are then ignored when one has been applied) and that the rules are taken into account in the order in which they appear in the `inf' file.
YAGLE -v adder adder_x
MBK_IN_LO
indicates the format of the input net-list.
spi for Spice net-list.
fne for Compass extracted net-list.
hns for Compass logical net-list.
al for Alliance extracted net-list.
vst for Vhdl structural description hns for Compass logical net-list
[WAR] Drain of transistor is not connected"
Indicates that a transistor drain which is connected to nothing has been
found in the circuit.
[WAR] Source of transistor is not connected"
Indicates that a transistor source which is connected to nothing has been
found in the circuit.
[WAR] Transistor used as a diode"
Indicates that a transistor with drain (or source) connected to gate has
been found in the circuit, and the signal connecting them is neither power
supply nor ground.
[WAR] Transistor used as a resistance"
Indicates that a transistor P (resp. N) with gate connected to the ground
(resp. power supply) has been found in the circuit.
[WAR] Transistor is always off"
Indicates that a transistor P (resp. N) with gate connected to power supply
(resp. ground) has been found in the circuit.
[WAR] Transistor used as a capacitance"
Indicates that a transistor with drain and source connected together has
been found in the circuit.
[WAR] Transistors are not used in the circuit"
This means that these transistor are not used to pull up or pull down any
transistor gate in the circuit, or any external port. This occurs if the
output of an inverter does not drive anything: In this case YAGLE considers
both transistors of the inverter to be unused.
[WAR] Connector unused"
This means that the external connector is neither the input nor the output
of any of the extracted transistor gates.
[WAR] Conflict may occur on signal"
This means that the signal may be pulled-up and pulled-down simultaneously.
This is a warning since this message may disappear with a greater
depth for the functional analysis process.
[WAR] HZ state may occur on signal"
This means that the signal is not pulled up or pulled down for every input
pattern on the cone entries. This is a warning since this message may
disappear with a greater depth for the functional analysis process.
[WAR] Signal does not drive anything"
This means that the transistor gate built on this signal neither attacks
any other transistor gate nor drives an external connector.
[WAR] Signal is not driven"
This means that the transistor gate built on this signal is not attacked
by either any other transistor gate or any external connector.
[WAR] Loop between 2 gates (nothing found)"
This means that a loop which does not correspond to a latch, bleeder or
bistable has been found in the circuit.
[ERR] Transistor gate signal is not driven"
Indicates that a transistor gate can not be pulled up or down.
[ERR] Transistor gate signal is not driven"
Indicates that a transistor gate can not be pulled up or down.
[ERR] Gate of transistor is not connected"
Indicates that a transistor gate which is connected to nothing has been
found in the circuit.
[ERR] No VDD connector in the circuit"
means that YAGLE did not find any external ports whose name is the name of
power supply in the circuit. Has CNS_VDDNAME the right value?
[ERR] No VSS connector in the circuit"
means that YAGLE did not find any external ports whose name is the name of
ground in the circuit. Has CNS_VSSNAME the right value?
[ERR] Connector is power supply and ground"
means that YAGLE found a connector whose name includes CNS_VDDNAME and
CNS_VSSNAME.
bop(1) , glop(1) , scmap(1) , c4map(1) , asimut(1) , proof(1) .
This tool is under development at the ASIM/LIP6/UPMC laboratory, cao-vlsi
research team.
We need your feedbak to improve documentation and tools.
If you find bugs, please fill-in the form at
http://asim.lip6.fr/alliance/support/bug-report/
Thanks for doing this.