alliance-support '2000
Re: help


Ludovic JACOMME (Ludovic.JACOMME@asim.lip6.fr)
Tue, 24 Oct 2000 17:54:05 +0200

Hi, On Sat, Oct 21, 2000 at 05:09:11PM +0200, hassan Ahmadi wrote: > please how can i translate this function in alliance > subset > > there was not implimented with "vasy" > > > entity A is > port ( a,x,y : in std_logic); > xout, yout : out std_logic)); > > end; > > architecture B of A is > > const K : signed(15 downto0) := > signed(To_StdLogicVector(x"2d00"); > > signal x1.., y1...,a1,...: signed (15 downto0); > begin > > if clk'vent and clk = '1' then > > if (a1(15) = '0' then > a2 <= a1 - signed(To_StdLogicVector(x"1680"); > x2 <= x1 + y2; > y2 <= y1 - x2; > end if; > ........ > > > thank you > ..... > > __________________________________________________________________ > Do You Yahoo!? > Gesendet von Yahoo! Mail - http://mail.yahoo.de > Yahoo! Mail auf Ihrem Handy? - http://mobil.yahoo.de If you want to use the signed VHDL type, you must include the IEEE.numeric_std package as follow : library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity hello is port( A ... ); end hello; If you want to declar a signed constant : ARCHITECTURE BEHAVIOR OF hello IS constant C0 : signed(15 downto 0) := X"2D00"; constant C1 : signed(15 downto 0) := X"1680"; ... You'd better replace the line : > a2 <= a1 - signed(To_StdLogicVector(x"1680"); by a2 <= a1 - C1; Regards, (_) ___ Ludovic JACOMME _ _ ( ) ( ) ( ) ( 6 ) Laboratoire LIP6, Equipe ASIM ( ) (_) ( _ ) Couloir 55-65, 2eme etage, ( )___ ( ) Universite P. et M. Curie (P6) (_____) (_) 4 place Jussieu, 75252 Paris Cedex 05 Tel: (33) 01.44.27.54.15 Fax: (33) 01.44.27.72.80 ICQ: 62526530 mailto: Ludovic.Jacomme@asim.lip6.fr http: //asim.lip6.fr/~ludo

 



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