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Name

lax - Parameter file for logic synthesis

Origin

This software belongs to the ALLIANCE CAD system from the CAO-VLSI team at ASIM/LIP6/UPMC laboratory.
LIP6/ASIM
University P. et M. Curie 4, place Jussieu 75252 PARIS Cedex 05 FRANCE
Fax : {33/0} 1.44.27.62.86
E-mail support : alliance-support@asim.lip6.fr

Synopsis

filename.lax

Description

The .lax file contains user modifiable parameters that lead to different logic synthesis.

Example

Circuit Interfce

-- Entity Declaration

ENTITY digia IS
PORT (

clock : in BIT;
-- clock
jour : in BIT;
-- jour
reset : in BIT;
-- reset
vdd
: in BIT; -- vdd
vss
: in BIT; -- vss i : in bit_vector(3 DOWNTO 0) ; -- i porte : out BIT; -- porte alarm : out BIT; -- alarm
ep_0 : out BIT;
-- ep_0
ep_1 : out BIT;
-- ep_1
ep_2 : out BIT;
-- ep_2
ep_3 : out BIT;
-- ep_3
ep_4 : out BIT;
-- ep_4
ep_5 : out BIT;
-- ep_5
ep_a : out BIT
-- ep_a ); END digia; -- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF digia IS

SIGNAL cs : REG_VECTOR(0 TO 2) REGISTER;
-- cs
SIGNAL cs_ea : BIT;
-- cs_ea
SIGNAL ef_ea : BIT;
-- ef_ea
SIGNAL cs_e5 : BIT;
-- cs_e5
SIGNAL ef_e5 : BIT;
-- ef_e5
SIGNAL cs_e4 : BIT;
-- cs_e4
SIGNAL ef_e4 : BIT;
-- ef_e4
SIGNAL cs_e3 : BIT;
-- cs_e3
SIGNAL ef_e3 : BIT;
-- ef_e3
SIGNAL cs_e2 : BIT;
-- cs_e2
SIGNAL ef_e2 : BIT;
-- ef_e2
SIGNAL cs_e1 : BIT;
-- cs_e1
SIGNAL ef_e1 : BIT;
-- ef_e1
SIGNAL cs_e0 : BIT;
-- cs_e0
SIGNAL ef_e0 : BIT;
-- ef_e0 SIGNAL ef : BIT_VECTOR(0 TO 2); -- ef
.Lax parameter file

## This line is a comment

## The following parameters are used in bop scmap and netoptim

## Set the Optimisation Mode (0..4)
## 0 : full area optimisation
## 2 : 50% area, 50% delay
## 4 : full delay optimisation
#M{4}

## Set the Optimisation Level (1..5)
## 1 : poor optimisation - small computation time ## 5 : best optimisation - long computation time #L{5}

## Set the list of delayed inputs
## This can be used to delay some primary inputs of ## the circuit. Delay is in ns (nano-seconds). ## Those signals are taken into account to optimise ## the global delay of the circuit.
#D{
i(3) :300;
i(0):100;
jour:120;
} ## Set the list of early outputs
## Some outputs may be critical. They can be ## optimized in delay before others regardless ## of the optimisation mode.
#E{
porte;
ep_3;
}

## Set the list of auxiliary (intermediate) signals to keep ## This can be used to decrease the memory consuption ## when trying to reorder Bdds. Those signals wont ## be reordered.
#S{
cs_ea;
ef_0;
ef_1;
ef_e4;
}

## The following parameters are used for whith C4

## Number of serial transistor in N-graph #N{4}

## Number of serial transistor in P-graph #P{4}

## The following parameters are used for whith netoptim ## (Delayed --#D--inputs are also used)

## Fanout factor : the max fanout of the ## output connector is multiplied by this factor #T{1000}

## Input Capacitance : The primary inputs of the circuit ## can have fanout values. (in fF)
#F{
jour:50;
}

## Output Capacitance : The primary outputs of the circuit ## can have capacitance. (in fF)
#C{
porte:50;
}

## Input Impedance (in Ohms)
#I{
jour:5000;
} ## Buffered Input : this is a list of primary inputs whith ## the number of buffer you want to add. #B{
clock:1;
}

See Also

bop(1) , glop(1) , scmap(1) , c4map(1) ,

Bug Report

This tool is under development at the ASIM/LIP6/UPMC laboratory, cao-vlsi research team.
We need your feedbak to improve documentation and tools. If you find bugs, please fill-in the form at http://asim.lip6.fr/alliance/support/bug-report/ Thanks for doing this.


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