We, at the Politechnic University at Madrid (Spain) are using Alliance in our course on Microelectronic design from 6 years ago, with versions 2.0 thru 3.0, 3.1 & up to 3.2. We also use other software from Altera & Cadence. Recently we think to move from a VHDL based course to a Verilog based one, cause cumbersome VHDL syntax seems to confuse students & also because spanish firms seem to prefer Verilog. Tools from Cadence & Altera support Verilog, so the question is ¿Would Alliance support Verilog in the future (or better, in the near future)? Thanks for your superb work. Greetings. -------------------------------------------------------------- - mcesar email: mcesar at sec dot upm dot es - PGP key available - Key Fingerprint: - RSA: D6B8 E631 D2CD 55D5 B281 AB01 929C 06BC - DH/DSS: A395 E0BE 39DE 89EC AE91 44CD 95AF 4DFC EAB2 FB31