lynx - Hierarchical netlist extractor
lynx [ -v ] [ -c ] [ -f ] [ -t ] input_name [ output_name ]
This software belongs to the ALLIANCE CAD system from the CAO-VLSI team at
ASIM/LIP6/UPMC laboratory.
LIP6/ASIM
University P. et M. Curie
4, place Jussieu
75252 PARIS Cedex 05
FRANCE
Fax : {33/0} 1.44.27.62.86
E-mail support : alliance-support@asim.lip6.fr
Lynx is a hierarchical layout extractor. It builds a netlist of interconnections from a symbolic layout view. The input argument is the name of the symbolic layout cell to be extracted, using as input format the one selected by the MBK_IN_PH(1) environment variable. If output is present, the resulting netlist will be given this name. If no output is given, then input will also be the generated netlist name. The output format is specified by the MBK_OUT_LO(1) environment variable. As most of the Alliance cad tools, lynx uses mbk(1) environment variables.
Lynx computes capacitances attached to the signals. At the moment, the value of these capacitances is computed for a typical one micron technology, and cannot be changed by the user through a technology file. The extracted netlist can be simulated for performance evaluation. The typical capacitances are given below in 10e-18 farad / lamda^2 :
Lynx checks the two basic ALLIANCE rules regarding connector names:
If two physical connectors are connected to the same net, they must
have the same name.
If two physical connectors have the same name, they must be internally
connected to the same net.
As a result only one logical connector will appear in the netlist. A
fatal error occurs if one of those two rules is violated ( even for power
and ground connectors )
When no options are specified, the current hierarchical level is extracted. The resulting netlist is the list of interconnections of the current layout hierarchy level. Three options are available to change lynx behaviour :
prompt> lynx -v amd2901
Gives a logical netlist of the chip amd2901, for one hierarchical
level, using verbose mode. This would be typically used to verify
the work of the ring(1)
router, in conjunction with lvx on the
specificated netlist and the extracted one.
prompt> cat $MBK_WORK_LIB/$MBK_CATAL_NAME
a2_y
a2p_y
.
.
prompt> lynx -f amd2901
Gives a logical netlist of the chip amd2901, after a flatten operation
stopping on the cells specified in the catalog ( the standard
cell library in our case ).
prompt> lynx -t amd2901
Gives a logical netlist of the amd2901 chip at the transistor
level. This is useful with yagle(1)
, to retrieve logical equations
from a layout.
al(1) , MBK_CATA_LIB(1) , MBK_WORK_LIB(1) , MBK_CATAL_NAME(1) , MBK_IN_PH(1) , catal(5) , RDS_TECHNO_NAME(1) .
This tool is under development at the ASIM/LIP6/UPMC laboratory, cao-vlsi
research team.
We need your feedbak to improve documentation and tools.
If you find bugs, please fill-in the form at
http://asim.lip6.fr/alliance/support/bug-report/
Thanks for doing this.