hi, I plan to use the alliance package. I have been through the help files but im not sure how can i use the package for my work. I have a few VHDL files in a heirarchical format where one VHDL file uses other VHDL files as components. I would like to know how can i flatten these files to form one single file using alliance. Thanks, Prashant Jain *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-* | Prashant Jain | * * | Residence: 50 Meadow Street, Apt. #37, | * Amherst, MA 01002. (413)-549-4897 * | | * Lab: 308, Knowles Engineering Building, * | Amherst, MA. (413)-545-0831 | *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*