alliance-support '2000
Re: more than one event 2


Ludovic JACOMME (Ludovic.JACOMME@asim.lip6.fr)
Thu, 2 Mar 2000 13:21:20 +0100

Hi Pierre Abbat, VASY is a prototype, and you don't have to take care of those warning messages ... (You're circuit won't oscillate :-) ) for this example you have to run : vasy -I vhdl -a codegen and VASY should generate a file codegen_v.vbe that can be used with Alliance. Regards, Ludo. On Tue, Feb 29, 2000 at 10:40:57AM -0500, Pierre Abbat wrote: > I fixed the illegal concurrent statements (I also got the same error when > leaving off the "end if" or the semicolon after it - the messages should be more > informative) and now I get the following: > > --> Run VHDL Compiler > --> Compile file codegen > onewait 1629 ERROR more than one event 2 > onewait 676 WARNING Possibility of an oscillation !! > onewait 679 Oscill : {0:0:1:u}({0:0:1:u}NOT(slipsync{0:0:1:u}) AND {0: > 0:1:u}NOT(clk{0:0:1:u}) AND > {0:0:1:u}(clk{0:0:1:u}'EVENT) AND {0:0:1:u}(slipsync{0:0:1:u}'EVENT)) > onewait 676 WARNING Possibility of an oscillation !! > onewait 679 Oscill : {0:0:1:u}({0:0:1:u}NOT(clk{0:0:1:u}) AND slipinte > rnal{0:0:1:u} AND {0:0:1:u}( > clk{0:0:1:u}'EVENT)) > onewait 1816 ERROR Some signals are missing in the sens list > onewait 676 WARNING Possibility of an oscillation !! > onewait 679 Oscill : {0:0:1:u}(carries{0:0:1:u}(0) AND {0:0:1:u}(slipc > lk{0:0:1:u}'EVENT) AND slipclk > {0:0:1:u}) > onewait 676 WARNING Possibility of an oscillation !! > onewait 679 Oscill : {0:0:1:u}({0:0:1:u}(slipclk{0:0:1:u}'EVENT) AND s > lipclk{0:0:1:u} AND carries > {1:1:1:u}(1)) > onewait 676 WARNING Possibility of an oscillation !! > onewait 679 Oscill : {0:0:1:u}({0:0:1:u}(slipclk{0:0:1:u}'EVENT) AND slipclk{0:0:1:u} AND carries > {3:3:1:u}(3)) > onewait 676 WARNING Possibility of an oscillation !! > onewait 679 Oscill : {0:0:1:u}({0:0:1:u}(slipclk{0:0:1:u}'EVENT) AND slipclk{0:0:1:u} AND carries > {4:4:1:u}(4)) > onewait 676 WARNING Possibility of an oscillation !! > onewait 679 Oscill : {0:0:1:u}({0:0:1:u}(slipclk{0:0:1:u}'EVENT) AND slipclk{0:0:1:u} AND carries > {5:5:1:u}(5)) > onewait 676 WARNING Possibility of an oscillation !! > onewait 679 Oscill : {0:0:1:u}({0:0:1:u}(slipclk{0:0:1:u}'EVENT) AND slipclk{0:0:1:u} AND carries > {6:6:1:u}(6)) > --> Drive Alliance file codegen_v > > I found the .v file partially written and the .vbe file untouched (they are in > that order in the Makefile). > > How do I get it to compile, and is it really going to oscillate? > > phma > -- A latch for a code generator, and other stuff related to direct-sequence spread spectrum > > > entity codegen is > port( > signal clk: in bit; -- Clock input at 76 MHz > signal din: in bit_vector(7 downto 0); -- Input from data lines of ROM > signal dout: out bit_vector(7 downto 0); -- Output to address lines of ROM > signal tifout: out bit; -- Transmitted intermediate frequency > signal clkout: out bit; > signal slipsync: in bit -- Edge causes chip clock to slip > ); > end codegen; > > architecture behavior of codegen is > signal latch: bit_vector(7 downto 0); > signal counter: bit_vector(6 downto 0); > signal carries: bit_vector(6 downto 0); > signal chipclk: bit; > signal slipclk: bit; -- clk with an occasional pulse removed > signal slipinternal: bit; > signal slopinternal: bit; > > begin > dout <= latch; > tifout <= counter(5); > clkout <= chipclk; > > state: process(chipclk) > begin > if (chipclk'event and chipclk) then > latch <= din; > end if; > end process state; > > slideclock: process(clk,slipsync) > begin > if (slipsync'event and not slipsync) then > slipinternal<=1; > end if; > if (clk'event and slipinternal and not clk) then > slopinternal<=1; > slipinternal<=0; > end if; > if (clk'event and slopinternal and not clk) then > slopinternal<=0; > end if; > slipclk<=clk and not slopinternal; > end process slideclock; > > count: process(slipclk) > begin > if (slipclk'event and slipclk) then > carries(0)<=1; > carries(6 downto 1)<=carries(5 downto 0) and counter(5 downto 0); > counter(6 downto 0)<=counter(6 downto 0) xor carries(6 downto 0); > chipclk<=counter(4); > end if; > end process count; > end behavior; > > > > (_) ___ Ludovic JACOMME _ _ ( ) ( ) ( ) ( 6 ) Laboratoire LIP6, Equipe ASIM ( ) (_) ( _ ) Couloir 55-65, 2eme etage, ( )___ ( ) Universite P. et M. Curie (P6) (_____) (_) 4 place Jussieu, 75252 Paris Cedex 05 Tel: (33) 01.44.27.54.15 Fax: (33) 01.44.27.72.80 ICQ: 62526530 mailto: Ludovic.Jacomme@asim.lip6.fr http: //asim.lip6.fr/~ludo

 



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