alliance-support '2000
Re: probleme de compilation


Ludovic JACOMME (Ludovic.JACOMME@asim.lip6.fr)
Fri, 21 Jan 2000 10:16:38 +0100

Hi ! > bonjour Mr > > j´ai essaye de compiler l´exemple suivant: > > ENTITY halfadder IS > PORT ( A, B, Vdd, Vss: IN BIT; > Sum, Carry: OUT BIT ); > END halfadder; > > ARCHITECTURE halfadder_data_flow OF halfadder IS > > SIGNAL A_bar, B_bar: BIT; > > BEGIN > > A_bar = NOT A; > B_bar = NOT B; > > Sum = ( A_bar AND B ) OR ( A AND B_bar ); > > Carry = A AND B; > > END halfadder_data_flow; > > j´obtient le resultat suivant: > > BEH : Compiling `halfadder.vbe` (Behaviour) ... > `halfadder.vbe` Error line 12 : parse error > `halfadder.vbe` Error 18 line 12 :illegal concurrent statement > `halfadder.vbe` Error line 13 : parse error > `halfadder.vbe` Error 18 line 13 :illegal concurrent statement > `halfadder.vbe` Error line 15 : parse error > `halfadder.vbe` Error 18 line 15 :illegal concurrent statement > `halfadder.vbe` Error line 17 : parse error > `halfadder.vbe` Error 18 line 17 :illegal concurrent statement > BEH : Error 40 :signal `carry` never assigned > BEH : Error 40 :signal `sum` never assigned > BEH : Error 40 :signal `b_bar` never assigned > BEH : Error 40 :signal `a_bar` never assigned > > svp qu´elle est la solution > ______________________________________________________ > Get Your Private, Free Email at http://www.hotmail.com En VHDL l'affectation d'un signal s'ecrit avec le symbol '<=' et pas '=' .... Sum <= ( A_bar AND B) OR (A AND B_bar); Regards, (_) ___ Ludovic JACOMME _ _ ( ) ( ) ( ) ( 6 ) Laboratoire LIP6, Equipe ASIM ( ) (_) ( _ ) Couloir 55-65, 2eme etage, ( )___ ( ) Universite P. et M. Curie (P6) (_____) (_) 4 place Jussieu, 75252 Paris Cedex 05 Tel: (33) 01.44.27.54.15 Fax: (33) 01.44.27.72.80 e-mail: Ludovic.Jacomme@asim.lip6.fr

 



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