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Capture and simulation of the behavioral view

Like we just saw, the capture of the behavioral view is the very first step of our design flow. Within Alliance, any VLSI design begins with a timing independent description of the circuit with a subset of VHDL behavior primitives. This subset of VHDL, called vbe, is fairly restricted: it is the data-flow subset of this language. It is not very easy to modelize an architecture using this subset, but it has the great advantage of allowing simulation, logic synthesis and bit level formal proof on the same files.

Patterns, VHDL simulation stimuli, are described in a specific formalism that can be captured using a dedicated language genpat. Once a VHDL behavioral description written and a set of test vectors have been determined, a functional simulation is ran. The behavioral VHDL simulator is called asimut. It validates the input behavior, according to the input/output vectors.



 



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