alliance-support '01
re: syf- problem


Iftekhar (nasreen@bttb.net.bd)
Fri, 8 Jun 2001 07:23:51 +0600

Dear, I have synchronous reset signal in my program. But still have the same problem. I have attached the file and the output of syf command (problem in jpg format). Please reply. > ----- Original Message ----- > From: Ludovic JACOMME <Ludovic.Jacomme@lip6.fr> > To: Iftekhar <nasreen@bttb.net.bd> > Cc: Alliance Support <alliance-support@asim.lip6.fr> > Sent: Monday, May 28, 2001 2:13 PM > Subject: Re: syf- problem > > > > Hi, > > > > > Dear Sir, > > > > > > I have little trouble with Syf tool. In my university we have Alliance > CAD > > > 3.2b version. There after generating VBE file from FSM, I wrote a > pattern > > > file. The pattern file is alright there and behaving as the FSM is > written. > > > > > > But in my PC I have Alliance CAD 4.0.6. Here generating VBE file from > the > > > same FSM I can't match that same pattern file. Not only that in my > version it > > > INVERSE THE POLARITY of different flags/output. If I use -I option to > stop > > > the inverse, still the pattern doesn't match. Here in the VBE file it > assign > > > a significant number of flag/out to '1' but in older version they are > assign > > > to some logic. Here it also removes a transition from one to another. > > > > > > Is it not correct that no matter what version I use the same pattern > file > > > should match without any modification of pattern file? How I know when > to use > > > -I ,-S this kind of option? > > > Why the old version is working properly? Why this kind of contradiction? > What > > > I am doing wrong? > > > > First of all, you should add a synchronous reset signal in your FSM > > Next you have to put a reset pattern sequence in your .pat file. > > (Enable reset signal during one cycle for example ...) > > > > --- FOR EXAMPLE > > ENTITY circuit is > > > > PORT > > > > > ck : in BIT; > > jour : in BIT; > > reset : in BIT; -- Synchronous reset signal > > i : in BIT_VECTOR(3 DOWNTO 0); > > porte : out BIT; > > alarm : out BIT > > ); > > END circuit; > > > > > > ARCHITECTURE FSM OF circuit is > > > > TYPE ETAT_TYPE IS (E0, E1, E2, E3, E4, E5, EA); > > > > SIGNAL EF, CS : ETAT_TYPE; > > > > CONSTANT digit0 : BIT_VECTOR (3 DOWNTO 0) := B"1111" ; -- O > > > > CONSTANT digit1 : BIT_VECTOR (3 DOWNTO 0) := B"0101" ; -- 5 > > CONSTANT digit2 : BIT_VECTOR (3 DOWNTO 0) := B"0011" ; -- 3 > > CONSTANT digit3 : BIT_VECTOR (3 DOWNTO 0) := B"1100" ; -- A > > CONSTANT digit4 : BIT_VECTOR (3 DOWNTO 0) := B"0001" ; -- 1 > > CONSTANT digit5 : BIT_VECTOR (3 DOWNTO 0) := B"0111" ; -- 7 > > --PRAGMA CURRENT_STATE CS > > --PRAGMA NEXT_STATE EF > > --PRAGMA CLOCK ck > > --PRAGMA FIRST_STATE E0 > > > > BEGIN > > > > > > PROCESS ( CS, i, jour, reset ) > > BEGIN > > CASE CS is > > WHEN E0 => > > porte <= '0'; > > alarm <= '0'; > > IF ( i = digit0 ) > > THEN > > IF ( jour = '1' ) > > THEN > > EF <= E5; > > ELSE > > EF <= EA; > > END IF; > > ELSE > > IF ( i = digit1 ) > > THEN > > EF <= E1; > > ELSE > > IF ( jour = '1' ) > > THEN > > EF <= E0; > > ELSE > > EF <= EA; > > END IF; > > END IF; > > END IF; > > > > .... > > > > END CASE; > > > > -- A synchronous reset condition > > -- on the next_state signal ... > > IF ( reset ='1') > > THEN EF <= E0; > > END IF; > > > > END PROCESS; > > > > PROCESS( ck ) > > BEGIN > > IF ( ck = '1' AND NOT ck'STABLE ) > > THEN > > CS <= EF; > > END IF; > > END PROCESS; > > > > END FSM; > > > > > > Waiting for your reply. > > > > > > > > > Mohammad Iftekhar Alam > > > > Best Regards, > > > > (_) ___ Ludovic JACOMME > > _ _ ( ) > > ( ) ( ) ( 6 ) Laboratoire LIP6, Equipe ASIM > > ( ) (_) ( _ ) Couloir 65-66, 4eme etage Porte 405, > > ( )___ ( ) Universite P. et M. Curie (P6) > > (_____) (_) 4 place Jussieu, 75252 Paris Cedex 05 > > > > Tel: (33) 01.44.27.27.06 > > 01.44.27.54.15 > > Fax: (33) 01.44.27.72.80 > > ICQ: 62526530 > > > > mailto: Ludovic.Jacomme@asim.lip6.fr > > http: file://asim.lip6.fr/~ludo > Error.jpg

 



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