The sclib library contains boolean functions, buffers, mux,
latches, flip-flops, (around 70 cells).
All the cells have the same height, share the power and ground lines
on east and west side, and have pitched I/Os in metal2 on north and
south side.
They are supposed to be used with a usual standard cells place and
route tool, such as Alliance's scr, Compass or
Cadence.
These cells are to be used primary for glue logic, since optimized
operators can be obtained using dedicated generators, as stated
paragraph 3.2.2.
The logic tool can map a behaviral VHDL onto this library.
The figure 3.2.1 below shows the difference between sclib and dplib regarding the shape and contents of a cell.
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