Good day! My name is Kotchubey Alexey. I'm a student of Dniepropetrovsk State University, Ukraine. I'm so sorry but I've got some problems with the Alliance CAD System 3.2b. We use this CAD for the practice on the university cource "Technologies of development and design of modern electronic devices". I wonder if you could send me some pieces of advice. My task with the CAD was to design a microchip that has function of time relay. It must have: - two 4-bit BCD inputs A and B that points to the stop of counting; - clock input (input for count); - enable input; - reset input. When reset='1' A and B inputs passes their information to the internal registers; - inverced latch output that switches to '0' when (B*10+A) clock leading edges have recieved. I have done steps: 1) VBE program making ("time_rele.vbe"); 2) compiling VBE with the Asimut; 3) making pattern file with the Genpat ("time_rele.c", "time_rele.pat"); 4) behavioral modeling with the Asimut (asimut -b time_rele time_rele r1) "r1.pat" - results; 5) optimization with the Bop and converting to .vst with the Scmap; (bop -o time_relecore time_relecorel; scmap time_relecorel time_relecorel) 6) optimization with the glop; (glop -g time_relecorel time_releopt -i -t; glop -f time_releopt time_releopt) 7) placement and routing with the scr (scr -p -r -l 5 -i 1000 time_releopt); 8) making genlib program, its compiling and executing (genlib -v time_relechip); So, I've got the structural description of destination microchip in the file "time_relechip.vst". When I tried to model this description with the Asimut (asimut time_relechip time_relechip r2), I got error messages about assert violation while writing data to internal registers mem1 and mem2 that are both connected with l2_y PADs. Not only I have got problems on this step but all my colleagues have with their projects. All files I have made and have got with Alliance tools I send you in zip archive time_rele.zip as file attachment. Thank you. With respect, Kotchubey Alexey.