alliance-support '01
Re: Minimal files needed for simulation and circuit size determination?


Ludovic JACOMME (Ludovic.JACOMME@asim.lip6.fr)
Wed, 31 Oct 2001 18:58:43 +0100

Hi, On Mon, Oct 29, 2001 at 01:04:13PM +0000, Neil Kenneally wrote: > Hi, > > >From just a '.vbe' and a '.pat' file I want to be able to > 1) simulate a circuit - I'm pretty sure this is possible yes of course. You write a .pat file and you simulate your behavioral description (vbe) using asimut tool. > 2) Get the circuit area it's a bit more complex. You have to map you vbe description using the scmap tool (see man page for details), and to place/route the resulting structural description using the scr tool (see man page, or tutorials for details) > > Can you tell me if this is possible without '.c' files? > > I'm interested in using an automatic process to drive the > optimisation of circuits (in terms of correct function, > speed and circuit area) from VHDL. > > Kind regards, > > Neil Best regards, (_) ___ Ludovic JACOMME _ _ ( ) ( ) ( ) ( 6 ) Laboratoire LIP6, Equipe ASIM ( ) (_) ( _ ) Couloir 65-66, 4eme etage Porte 405, ( )___ ( ) Universite P. et M. Curie (P6) (_____) (_) 4 place Jussieu, 75252 Paris Cedex 05 Tel: (33) 01.44.27.27.06 01.44.27.54.15 Fax: (33) 01.44.27.72.80 ICQ: 62526530 mailto: Ludovic.Jacomme@asim.lip6.fr http: //www-asim.lip6.fr/~ludo

 



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