Table of Contents

Name

bsg - Barrel Shifter Generator

Synopsys

bsg bits [ -virtual ] [ -msb0 ]
[ -layout ] [ -icon ] [ -vhdl ] [ -patterns ] [ -datasheet ] [ -physical_box ] [ -logical_box ]
[ -o name_prefix ]

Origin

This software belongs to the ALLIANCE CAD system from the CAO-VLSI team at ASIM/LIP6/UPMC laboratory.
LIP6/ASIM
University P. et M. Curie 4, place Jussieu 75252 PARIS Cedex 05 FRANCE
Fax : {33/0} 1.44.27.62.86
E-mail support : alliance-support@asim.lip6.fr

Description

bsg is a fast barrel shifter generator for bit-sliced data-paths. The slice is fixed to 60 lambdas, allows virtual terminals, and could be used with the data-path compiler fitpath(1) . It has the capability of doing logical and arithmetical shifts and rotations. fitpath(1) .

The generator needs a leaf cell library to work well. The MBK_CATA_LIB(1) environment variable should contain the path to the generator library, bslib.

Options

bits
data size in bits of the barrel shifter to be generated. Must be in range 3-64. This argument is mandatory. -virtual Generates a barrel shifter with virtual connectors, as opposed to the default that generates steady terminals, to be used by the data-path compiler fitpath(1) .
-msb0
Index 0 of vectorized busses will be used for the most significant bit, else index 0 will be used for the less significant bit of busses.
-layout
To obtain a layout view. The different formats are given by mbk(1) documentation.
-icon
To obtain a icon view.
-vhdl
To obtain a VHDL data-flow behavioral description view.
-patterns
To obtain a patterns file.
-datasheet
To obtain a data sheet.
-physical_box
To obtain a physical outline view. Cannot be used with the -layout option. The different formats are given by mbk(1) documentation.
-logical_box
To obtain a netlist view. This view contains only the logical block interface. The different formats are given by mbk(1) documentation.
-o blockname
blockname indicate the user name prefix for all files generated. If no name is given, a default name will be composed by the generator. For each set of parameters and options, the default name will be different.

Each signal name is predefined and can not be modified by the user. bits represent the number of bits. Signal names are:

in_s[0..bits-1]
Shift number.
in_d[0..bits-1]
Data input.
out_d[0..bits-1]
Data output.
left
When set to logical 1, Makes a shift to the left. When set to ground, makes a shift to the right.
rot
When set to logical 1, makes a rotation which direction depends on the value of the left signal.
ext
When set to logical 1 whenever left is set to logical 0 (right shift) and rot to logical 0 (no rotation), makes an arithmetical shift to the right (lefting in_d[bits-1] in the most significant bits).

rot left ext action
0 0 0 logical right shift 0 0 1 arithmetical right shift 0 1 0 logical left shift 0 1 1 arithmetical left shift 1 0 0 right rotation
1 0 1 ?
1 1 0 left rotation
1 1 1 ?

See the Barrel Shifter Cell Library documentation for more details about the shifter structure and connectors.

Output Files

name.xx
The layout and netlist views. The suffix depends on the MBK_OUT_PH and MBK_OUT_LO environment variables. (see below).
name.icn
The shifter icon view.
name.vbe
The VHDL behavioral view of the shifter.
name.pat
The patterns set.

Environment Variables

MBK_CATA_LIB
contains the directory path of the barrel shifter leaf cells library. This library is already in /labo/cells/bsg and if not, depends upon the system administrator installation.
MBK_WORK_LIB
contains the directory path of the working directory. Usually set to ..
MBK_IN_PH
contains the format of the barrel shifter cell library.
MBK_OUT_PH
contains the desired format of the layout output.
MBK_OUT_LO
contains the desired format of the netlist output.

See Also

MBK_CATA_LIB(1) ,
MBK_WORK_LIB(1) , MBK_IN_PH(1) , MBK_OUT_PH(1) , MBK_OUT_LO(1) , mbk(1) , genlib(1) , vhdl(1) , fitpath(1) , rfg(1) , grog(1) , rsa(1) .

Bug Report

This tool is under development at the ASIM/LIP6/UPMC laboratory, cao-vlsi research team.
We need your feedbak to improve documentation and tools. If you find bugs, please fill-in the form at http://asim.lip6.fr/alliance/support/bug-report/ Thanks for doing this.


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