alliance-support '1999
quick help


Perry Mages (mages@cig.mot.com)
Tue, 26 Jan 1999 16:33:56 -0600 (CST)

Ok, I have a VHDL file. Let's call it proj1.vhdl. How do I compile it and run it through your simulator for a period of 100ns. Here is the VHDL file: (I used it fine with synopsys) ------------------------------------------------------------------------ entity proj1 is end proj1; library ieee; use ieee.std_logic_1164.all; architecture test of proj1 is -- signal definitions signal enable: std_logic := '0'; signal clear: std_logic := '0'; signal output0: std_logic := '0'; signal output1: std_logic := '0'; signal clock: std_logic := '0'; begin clock <= not clock after 5 ns; counter: process(clock, enable, clear, output0, output1) begin if rising_edge(clock) then if clear = '1' then -- clear the output output0 <= '0' after 8 ns; output1 <= '0' after 8 ns; elsif enable = '1' then -- increment counter output0 <= not output0 after 8 ns; if output0 = '1' then output1 <= not output1 after 8 ns; end if; end if; end if; end process counter; end test; ---------------------------------------------------------------- thanks, Perry -- You have just received mail from: Perry Z. Mages mages@cig.mot.com Your smiley face is: ^v^v^ mountains [Kenneth P. Brooks, <CSD.BROOKS at SU-SCORE>]

 



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