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Name

YAGLE - Functional abstraction of CMOS circuits

Origin

This software belongs to the ALLIANCE CAD system from the CAO-VLSI team at ASIM/LIP6/UPMC laboratory.
LIP6/ASIM
University P. et M. Curie 4, place Jussieu 75252 PARIS Cedex 05 FRANCE
Fax : {33/0} 1.44.27.62.86
E-mail support : alliance-support@asim.lip6.fr

Synopsis

YAGLE [-v] [-d] [-b] [-z] [-nc] [-nh] [-p=n] [-fcl] [-i] [-os] [-t] file1 [file2]

Description

YAGLE is a functional abstractor for CMOS digital circuits. It provides a VHDL data flow description from a transistor level description of the circuit. The transistor net-list can be flat or hierarchical. The VHDL subset generated by YAGLE is supported by ASIMUT, BOP, SCMAP and PROOF. Tri-state nodes of the circuit are expressed as VHDL Bus. Latches and registers are expressed as VHDL Register signal. Yagle does not use a predefined gate library except for latches and flip-flops. All styles or circuitry are supported: dual-cmos, precharge, pass-transistor... All power supplies and grounds signals must be connected to an external connector.
In a first phase, YAGLE extracts the CMOS dual circuitry. In a second phase, YAGLE builds the gate net-list for the remaining circuitry whilst performing functional analysis in parallel, in order to prevent the fabrication of false branches within a gate and to verify the behaviour of the gate.
This functional analysis depends on the `n' parameter that defines the maximum depth (in gates) of the analysis.

Options

Options may be given in any order before or after the filename(s).

file2
is the name of the vbe file to be generated. File1 is the default value.
-v
When this option is set, the interface and the internal signal of the behavioural description are vectorised. Every bit of the vector has to be of the same type (in, out...for instance) otherwise the functional description will not be generated.
-d
YAGLE generates a `cns' file which contains the flat gate netlist. This file is mainly used for debugging.
-b
YAGLE orients transistors using a simple rule: A transistor whose source is connected to the output of a CMOS Duals gate, and not connected to a transistor gate, is oriented form source to drain. This orientation is performed during the phase of extraction of CMOS duals.
-z
When this option is set, YAGLE exploits high impedance nodes during the phase of functional analysis. This allows, for example, the resolution of false conflicts in circuits which use precharge logic.
-nc
Disables the detection of complex gates. Without this option complex gates such as edge-triggered flip-flops are identified by pattern-matching applied to the disassembled gate net-list. Special predefined behavioural descriptions are then generated for these gates. This option is useful if a one to one correspondance between the elements of the behavioural description and the elements of the disassembled gate net-list is required.
-nh
YAGLE generates a gate level net-list. The variable MBK_OUT_LO has to be set to choose the format of the out files: the netlist and the gates. A behavioural description is generated for each gate.
-p=n
This option sets the maximum depth for the functional analysis. This is the depth of circuitry (in gates) taken into account when detecting reconvergences in the circuit. The default value is 5. When n=0, the functional analysis process is disabled.
-os
This option provides only one power supply and ground connector in the interface of the behavioural description. This can be usefull in order to use Asimut or Proof since there may be only one in the specification, and more in the circuit to be abstracted. When this option is set, the name of power supply an ground are given by MBK_VDD and MBK_VSS.
-fcl
This option makes YAGLE use library-based transistor netlist recognition. This allows the user to specify a number of netlists to be identified within the circuit to be disassembled. These netlists are specified in the Spice format and can contain a number of special directives for the marking of the identified signals and transistors in the circuit, for example signals corresponding to memory points or transistors to be ignored.

In addition the user can specify a behavioural description for the transistor netlist in the .vbe format (see man vbe) which is used to generate the global behavioural description of the circuit. This allows the functional abstraction of circuits containing analog blocks for example RAMs containing sense amplifiers.

-i
This option makes YAGLE read the `inf' file. This file should have the same name than the input file and inf for extension. It may contain mutual exclusion conditions on ports of the circuit. These conditions are only used in the functional analysis process. # lines beginning with `#' are comment lines
#
Syntax for the mutual exclusion conditions MUTEX muxUP{a,...,d}; muxDN{m,...,p}; cmpUP{i,...,l}; cmpDN{x,...,z}; END
muxUP
expresses that one port at most in the list is one".
muxDN
expresses that one port at most in the list is zero".
cmpUP
expresses that one and only one port in the list is one".
cmpDN
expresses that one and only one port in the list is zero".

Port name may be preceded by the character `~' which minds that it is the inverse of the port which has to be taken into account.

The user can also use this file to rename internal signals in the behavioural description in order to use the formal proof.

#
Syntax to rename signals for the behavioural description RENAME existing_name : new_name ; *gno* : *latch_data* ; END

new_name will replace existing_name in the behavioural description file. It is possible to use the joker `*'. When the names contain the string gno", this string is replaced by the string latch_data (l2_y_gno_01 is replaced by l2_y_latch_data_01).

Beware that only one rule can be applied to a name, (the following rules are then ignored when one has been applied) and that the rules are taken into account in the order in which they appear in the `inf' file.

-t
Set the trace mode during functional analysis.

Example

YAGLE -v adder adder_x

Output Files

vbe
The functional description is described in a file called file1 or file2, with extension .vbe.
cns
The disassembled gate net-list or cone net-list description when the `-d' option is set.
vst/hns
The structural description when the `-nh' option is set.
rep
Errors and warnings are reported in a file with extension .rep.

Environment Variables

MBK_IN_LO
indicates the format of the input net-list.

spi for Spice net-list.
fne for Compass extracted net-list. hns for Compass logical net-list. al for Alliance extracted net-list.

MBK_OUT_LO
indicates the format of the output net-list when the `nh' option is set. MBK_IN_LO may take the value

vst for Vhdl structural description hns for Compass logical net-list

MBK_WORK_LIB
Indicates where YAGLE has to read the input file and write the resulting files.
MBK_CATA_LIB
If the input net-list is hierarchical, the leaf cells may not be in the working directory MBK_WORK_LIB. In that case, MBK_CATA_LIB indicates where YAGLE can find the cells.
CNS_VDDNAME
Sets the name of power supply. vdd is the default. Every external port of the circuit whose name contain this string will be considered as a power supply.
CNS_VSSNAME
Sets the name of the ground. vss is the default. Every external port of the circuit whose name contain this string will be considered as a ground.
CNS_GRIDNAME
Sets the name of the grid connector of a transistor. grid is the default.
CNS_SOURCENAME
Sets the name of the source connector of a transistor. source is the default.
CNS_DRAINNAME
Sets the name of the drain connector of a transistor. drain is the default.
ELP_TECHNO_NAME
Sets the full access path and name of the technology file (.elp) used to correct the node capacitances in the circuit.
VH_BEHSFX
Sets the extension of the file that will contain the VHDL description. vbe is the default value.
YAGLE_LANGUAGE
When set to F, YAGLE will report errors and warnings in French. When set to E, YAGLE will report errors and warnings in English. The default is English.
YAGLE_STAT_MODE
When set to Y, YAGLE generates a file with the extension .stat which contains statistics of the transistor net-list.
YAGLE_MAX_LINKS
Sets the the maximum possible length of a branch within a gate. The default is six.

Diagnostics

[WAR] Drain of transistor is not connected" Indicates that a transistor drain which is connected to nothing has been found in the circuit.
[WAR] Source of transistor is not connected" Indicates that a transistor source which is connected to nothing has been found in the circuit.
[WAR] Transistor used as a diode"
Indicates that a transistor with drain (or source) connected to gate has been found in the circuit, and the signal connecting them is neither power supply nor ground.
[WAR] Transistor used as a resistance" Indicates that a transistor P (resp. N) with gate connected to the ground (resp. power supply) has been found in the circuit. [WAR] Transistor is always off"
Indicates that a transistor P (resp. N) with gate connected to power supply (resp. ground) has been found in the circuit. [WAR] Transistor used as a capacitance" Indicates that a transistor with drain and source connected together has been found in the circuit.
[WAR] Transistors are not used in the circuit"

This means that these transistor are not used to pull up or pull down any transistor gate in the circuit, or any external port. This occurs if the output of an inverter does not drive anything: In this case YAGLE considers both transistors of the inverter to be unused. [WAR] Connector unused"
This means that the external connector is neither the input nor the output of any of the extracted transistor gates. [WAR] Conflict may occur on signal"
This means that the signal may be pulled-up and pulled-down simultaneously. This is a warning since this message may disappear with a greater depth for the functional analysis process. [WAR] HZ state may occur on signal"
This means that the signal is not pulled up or pulled down for every input pattern on the cone entries. This is a warning since this message may disappear with a greater depth for the functional analysis process. [WAR] Signal does not drive anything" This means that the transistor gate built on this signal neither attacks any other transistor gate nor drives an external connector. [WAR] Signal is not driven"
This means that the transistor gate built on this signal is not attacked by either any other transistor gate or any external connector. [WAR] Loop between 2 gates (nothing found)" This means that a loop which does not correspond to a latch, bleeder or bistable has been found in the circuit. [ERR] Transistor gate signal is not driven" Indicates that a transistor gate can not be pulled up or down. [ERR] Transistor gate signal is not driven" Indicates that a transistor gate can not be pulled up or down. [ERR] Gate of transistor is not connected" Indicates that a transistor gate which is connected to nothing has been found in the circuit.
[ERR] No VDD connector in the circuit" means that YAGLE did not find any external ports whose name is the name of power supply in the circuit. Has CNS_VDDNAME the right value? [ERR] No VSS connector in the circuit" means that YAGLE did not find any external ports whose name is the name of ground in the circuit. Has CNS_VSSNAME the right value? [ERR] Connector is power supply and ground" means that YAGLE found a connector whose name includes CNS_VDDNAME and CNS_VSSNAME.

See Also

bop(1) , glop(1) , scmap(1) , c4map(1) , asimut(1) , proof(1) .

Bug Report

This tool is under development at the ASIM/LIP6/UPMC laboratory, cao-vlsi research team.
We need your feedbak to improve documentation and tools. If you find bugs, please fill-in the form at http://asim.lip6.fr/alliance/support/bug-report/ Thanks for doing this.


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