AMG - Array Multiplior Generator
This software belongs to the ALLIANCE CAD system from the CAO-VLSI team at
ASIM/LIP6/UPMC laboratory.
LIP6/ASIM
University P. et M. Curie
4, place Jussieu
75252 PARIS Cedex 05
FRANCE
Fax : {33/0} 1.44.27.62.86
E-mail support : alliance-support@asim.lip6.fr
amg <size1> <size2> [ -t0 -t1 -n=<integer> ] [ -virtual -msb0 ] [ -layout -vhdl -datasheet -icon -patterns] [ -o <BlockName> ]
amg provides several different views of a booth multiplier with or without pipeline. The multiplier generated respects a bit-slice topologie and can be inserted in a data path.
The Interface is the following
unpipelined multiplier:
ENTITY amg IS
pipelined multiplier:
ENTITY amg IS
PORT ( a: IN BIT_VECTOR (M-1 DOWNTO 0),
b: IN BIT_VECTOR (N-1 DOWNTO 0),
p: OUT BIT_VECTOR ((N+M-1) DOWNTO 0),
ck: IN BIT,
sd: IN BIT,
st: IN BIT,
Vss: IN BIT );
END amg;
The global topologie is the following
As it can be seen on the figure, the multiplier can be divided
into three parts:
-> The input part is the DNC part.
-> The central part is a succession of mux column and csa
column".
-> The output part is the final adder of the multiplication.
t0: This parameter indicates if a master-slave column must
be placed after the first part.
* t0 -> after
* default -> none
t1: This parameter indicates if a master-slave column must
be placed before the CLA.
* t1 -> before
* default -> none
n: This parameter indicates the number of master-slave columns in the central part
amg 32 32 -t0 -t1 -n=3 -layout -datasheet -vhdl -o mult32
Produces the layout, the datasheet, and the vhdl view of a 32 X 32 size multiplier with pipeline.
MBK_CATA_LIB(1) , MBK_WORK_LIB(1) , MBK_OUT_PH(1) , MBK_OUT_LO(1) , MBK_IN_PH(1) ,
This tool is under development at the ASIM/LIP6/UPMC laboratory, cao-vlsi
research team.
We need your feedbak to improve documentation and tools.
If you find bugs, please fill-in the form at
http://asim.lip6.fr/alliance/support/bug-report/
Thanks for doing this.