Dear sirs, I have installed Alliance v. 4.0.6 and I tried to use the graphic layout editor GRAAL. I found out several errors in the technology files. I solved them by commenting the following environment variable: DREAL_TECHNO_NAME GRAAL_TECHNO_NAME GENVIEW_TECHNO_NAME RDS_TECHNO_NAME ELP_TECHNO_NAME In this way Graal runs perfectly, however I would like two know which design rules are used by default by the tool when no one is specified in the configuration file. Also, I would like to implement some CPL gates in a 0.8um technology so I wonder if you have avalaible some bug-free technology files (.rds, .elp, .genview, .dreal and .graal). If not I would like to know the exact rules to create the aforementioned files by myself. Finally I would like to know if it is possible to layout multigate transistors (I don't have seen any option in the menu bars). Thank for your kind attention. Sincerely, --Gianluca Cornetta -- ------------------------------------------------------------ O O O U P C Gianluca Cornetta O O O Departement of Computer Architecture O O O D A C Universitat Politecnica de Catalunya Campus Nord. Modul C6 (room S103) Gran Capita' s/num. 08071 - BARCELONA e-mail: cornetta@ac.upc.es phone : +34-3-4011649 fax : +34-3-4017055 ------------------------------------------------------------