alliance-users '1997
Questions about Alliance


Boulis Athanassios (thanos@ced.tuc.gr)
Mon, 9 Jun 1997 12:07:30 +0300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - This message is sent to the hundreds of members of the "alliance@masi.ibp.fr" mailing-list all through the world. Please don't bother them with administrative requests such as 'help', 'subscribe', 'unsubscribe'... Instead, use the adress "alliance-request@masi.ibp.fr" for such administrative requests. If you feel the absolute need to talk to an human, use the adress 'cao-vlsi@masi.ibp.fr'. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Dear Sirs, I am using Alliance to implement, test and simulate a systolic array of processors for my diploma thesis. As I have nobody to help me (except the man pages) I am just experimenting with the tools. Consequently I have some questions to ask you: 1) Let's say that I have a .vst file with several sub- components that end up to leaves which are .vbe files. In order to compile the .vst file you have to place the name of the directory which contains the .vbe files into the env. variable MBK_CATA_LIB and create a CATAL file in that directory that contains the names of the .vbe files. I've tried it and it worked. Is there anything else about that (or another way) ? 2) When I run the SCR tool with .al files and then I see the resulting .ap file with the graal visual editor, I see only the border of the basic cells, their inputs, outputs, vss, vdd and NOT the contains of each cell. In the contrary when I open the a2_y.ap file from the scr library I see all the parts of the cell. Can I fix that ? (and see all the parts). Something more: In my .ap files I see also a strip of a Talu2 running vertically the cell, what is that, and what does T stands for ? 3) Most Important: I 'd like to build a CMOS switch as shown in the figure below and use it later in structural descriptions. | | not( SEL ) pMOS O ( I made the figure using notepad ) ------- ( and I don't know how it may look to you) A_____| |_____B | | ------- nMOS | | SEL I though of designing it in graphically in graal and then using lynx and desp to get the .al and .vbe files. Is that good enough ? Must the cell have the same height as the other cells of the standard library or I can avoid that? 4) I use also the Tas tool. I built a file (my_and.vbe) and with Logic I got the .al file. Then I ran the Tas tool with a -x option. I got a .ttv file, a part of which I copy here. I've read the man pages. What does input_commutation, output_commutation and delay resistance slope mean ? What is the intermediate signal c.mbk_sig2 ? T X b c ( (* (DD 1274 2.32 382)) # DOWN(b) = UP(c.mbk_sig2), Tp=880 pS # UP(c.mbk_sig2) = DOWN(c), Tp=394 pS (* (UU 1111 2.09 316)) # UP(b) = DOWN(c.mbk_sig2), Tp=586 pS # DOWN(c.mbk_sig2) = UP(c), Tp=525 pS ); 5) I've noticed that there are two kinds of library cells (with fanout 1 and 2). Can I use a fanout 2 gate to drive 4 other gates? Is there going to be another effect except the increased delay? (due to increased output capacitance). 6) If I want to give directions to the scr tool, to place some cells in a 2-dimentional array, how can I do it ? (the man pages weren't illuminating at all). NOTE: I can't use for the moment the genlib tool, or any other tool that uses the C functions Loins, Logon etc.. due to problems with the library formats. Thank you in advance for your attention. Thanassis Boulis VLSI lab, Technical University of Crete Please reply to: siaper@ced.tuc.gr including the word 'Boulis' in the text or subject AND to: vlsi@tarra.ced.tuc.gr -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - END-OF-MAIL

 



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