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One of our main goal is process independence. The process independence relies on a symbolic layout approach and a fully automatic process mapping from a silicon supplier to another. The existing portable libraries are designed for standard CMOS process with one poly and two metals. New high performance library is being designed. Besides providing VLSI CAD tools with their own portable cells libraries, we are also aware of industry standard CAD systems, this is why we want to provide design kits for Cadence and Synopsys. Some of these kits are still under develloppement, so check ftp://asim.lip6.fr/pub/alliance/design-kits/ often for avaibility.
Cadence
Design Kit for the portable, process independent Alliance
Standard Cells Libraries :
The Cadence DesignKit allows the design of a complete
VLSI chip that can be fabricated by several silicon
foundries, thanks to the symbolic layout approach. The
DesignKit includes parametrization of the Cadence tools
for layout design (virtuso), place/route (Cell Ensemble),
DRC, netlist extraction (spice format), LVS (diva),
functional simulation (Verilog-XL), timing analysis
(veritime),...The Cadence-Alliance DesignKit is supported
by the 97a version of the Cadence Design Framework II,
and is available for free.