alliance-support '2000
Re: std_logic versus bit


Ludovic JACOMME (Ludovic.JACOMME@asim.lip6.fr)
Mon, 21 Feb 2000 18:29:46 +0100

Hi, Alliance VHDL subset is very particular (see man pages vbe(5) and vst(5)) But to answer your question : Bit is a standard basic type of VHDL (it can takes only 2 values : ( '0' or '1') std_logic is a standard VHDL type defined by IEEE in synthesis package std_logic_1164 (see http://www.vhdl.org/vi/vhdlsynth/siwg/ for details). A signal of type std_ulogic can take 9 values : TYPE std_ulogic IS ( 'U', -- Uninitialized 'X', -- Forcing Unknown '0', -- Forcing 0 '1', -- Forcing 1 'Z', -- High Impedance 'W', -- Weak Unknown 'L', -- Weak 0 'H', -- Weak 1 '-' -- Don't care ); It's very usefull to describe tristate gates (with 'Z' value), pull-up, pull-down ('L' and 'H') or to test uninitialized registers during simulation ('U', 'X') or to indicate don't cares values to synthesis tool ('-'). Unfortunately Alliance doesn't support this VHDL type. On Fri, Feb 18, 2000 at 12:31:40PM -0500, Pierre Abbat wrote: > What's the difference between std_logic and bit in VHDL? The VHDL tutorial I > found on the Net uses std_logic, but Alliance uses bit. > > phma Hope this help, Ludo. (_) ___ Ludovic JACOMME _ _ ( ) ( ) ( ) ( 6 ) Laboratoire LIP6, Equipe ASIM ( ) (_) ( _ ) Couloir 55-65, 2eme etage, ( )___ ( ) Universite P. et M. Curie (P6) (_____) (_) 4 place Jussieu, 75252 Paris Cedex 05 Tel: (33) 01.44.27.54.15 Fax: (33) 01.44.27.72.80 ICQ: 62526530 mailto: Ludovic.Jacomme@asim.lip6.fr http: //asim.lip6.fr/~ludo

 



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