This software belongs to the ALLIANCE CAD system from the CAO-VLSI team at
ASIM/LIP6/UPMC laboratory.
LIP6/ASIM
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FRANCE
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E-mail support : alliance-support@asim.lip6.fr
DP_MUX5CS - 5 input multiplexer.
#include <fpgen.h>
void DP_MUX5CS(
char *InstName, /* Instance name */
long Width , /* Number of bits */
long Slice , /* Index of the bottom slice */
char *BusSel , /* IN Input Select CTRL */ char *BusI4 , /* IN Third Input DATA */ char *BusI3 , /* IN Third Input DATA */ char *BusI2 , /* IN Third Input DATA */ char *BusI1 , /* IN Second Input DATA */ char *BusI0 , /* IN First Input DATA */
DP_MUX5CS creates a 5 input multiplexer. It is build using a dual-CMOS
architecture. The signal BusSel select which input is connected to the
output :
- BusSel equal 000":BusO <= BusI0.
- BusSel equal 001":BusO <= BusI1.
- BusSel equal 010":BusO <= BusI2.
- BusSel equal 011":BusO <= BusI3.
- BusSel equal 100":BusO <= BusI4.
DP_MUX3CS build an operator of Width bits and then instanciates it
with the name InstName. The maximal authorized value for Width is the full
width of the current data-path, set by the previous call to the function
DP_DEFLOFIG. In the layout the leaf cells are placed on the slices numbered
from Slice to Slice+Width-1 (the bottom slice of the whole data-path
is numbered zero).
Operator wide : 86 lambdas.
DP_MUX5CS("mux5cs_instance0", 32,
0, bus_sel[2:0] , input_i4[31:0]", input_i3[31:0]", input_i2[31:0]", input_i1[31:0]", input_i0[31:0]", output_o[31:0]", EOL);
fpgen(1) , dpr(1) , genlib(1) , mbk(1) , DP_DEFLOFIG(3) , DP_SAVLOFIG(3) , DP_LOCON(3) , DP_IMPORT(3) , DP_INV(3) , DP_BUSE(3) , DP_AND2(3) , DP_NAND2(3) , DP_AND3(3) , DP_NAND3(3) , DP_OR2(3) , DP_NOR2(3) , DP_OR3(3) , DP_NOR3(3) , DP_XOR2(3) , DP_XNOR2(3) , DP_NAND2MASK(3) , DP_NOR2MASK(3) , DP_XNOR2MASK(3) , DP_CONST(3) , DP_NMUX2CS(3) , DP_MUX2CS(3) , DP_MUX3CS(3) , DP_MUX4CS(3) , DP_MUX5CS(3) , DP_BUSE(3) , DP_NBUSE(3) , DP_ADD2F(3) , DP_ADSB2F(3) , DP_SHIFT(3) , DP_MULT(3) , DP_MULTP(3) , DP_NUL(3) , DP_PDFF(3) , DP_PDFFR(3) , DP_PDFFT(3) , DP_PDFFRT(3) , DP_RFG1C0(3) , DP_RFG1CC(3) , DP_RFG2C0(3) , DP_RFG2CC(3) ,
This tool is under development at the ASIM/LIP6/UPMC laboratory, cao-vlsi
research team.
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