alliance-support '2000
Problem with alliance


Wilfried Tenten (wilfried.tenten@de.bosch.com)
Tue, 21 Mar 2000 11:05:53 +0100

Hello Mr. Jacomme, I have installed the alliance software 4.06 and there some problems with the tutorials arose: 1. using vasy [11] Wilfried > make MBK_WORK_LIB=.; export MBK_WORK_LIB; MBK_CATAL_NAME=NO_CATAL; export MBK_CATAL_NAME; /usr1/projects/gnu/alliance-4.0.6/archi/Solaris/bin/vasy -a -I vhdl -H hadamard @@@@ @@@ @ @@@@ @ @@@@ @@@@ @@ @ @ @ @@ @@ @ @@ @ @@@ @@ @ @@ @ @@ @ @@@ @@@ @@ @ @@ @ @ @@ @@@@ @@ @@ @ @ @@ @@@@ @@ @@ @ @ @@ @@@ @@ @@@ @@@@@@@ @ @@ @@ @@@ @ @@ @@ @@ @@ @ @ @@ @@@ @ @@ @ @@@@ @@@@ @ @@@@ @@@@@@ VHDL Analysis for Synthesizer Alliance CAD System 4.0.6, vasy 1.05 Copyright (c) 1999-2000, ASIM/LIP6/UPMC Author(s): Ludovic Jacomme Contributor(s): Frederic Petrot E-mail support: alliance-support@asim.lip6.fr vasy [Options] Input_name Output_name Options : -D [Level] [File] Sets Debug mode on -V Sets Verbose mode on -I [extention] Input file format -S Uses Std_logic instead of Bit -i Drives initials values -v Verilog output -a Alliance output -s Standard VHDL output -r Rtl output make: *** [hadamard.vst] Error 1 I am not shure, but I believe that there is a problem with the -H hadamard [14] Wilfried > make @@@@ @ @@@@ @ @ @@ @@ @@ @@ @ @@ @ @@@ @@ @ @@@ @@ @@@ @@@@ @@@ @@@ @@@@ @@ @@@ @@ @@ @@ @ @@@ @@ @@@@ @@ @@ @@ @@ @@ @@ @@ @@ @@@ @@ @@ @@ @@ @@@@@ @@ @@ @ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @ @@ @@ @@ @@ @@ @@ @@ @@@ @ @@ @@ @@ @@ @@ @@ @@@ @@@ @@ @ @@@@ @@@@ @@@@ @@@ @@@ @@@@ @@ @@ @@@ @@ @@@@ Mapping Standard Cells Alliance CAD System 4.0.6, scmap 4.0.9 [1999/11/09] Copyright (c) 1990-2000, ASIM/LIP6/UPMC E-mail support: alliance-support@asim.lip6.fr Load param on 'area.lax' done ... ================================ Environment ================================ MBK_WORK_LIB = . MBK_CATA_LIB = .:/usr1/projects/gnu/alliance-4.0.6/archi/Solaris/cells/sxlib:/usr1/projects/gnu/alliance-4.0.6/archi/Solaris/cells/padlib MBK_TARGET_LIB = /usr1/projects/gnu/alliance-4.0.6/archi/Solaris/cells/sxlib MBK_IN_LO = vst MBK_OUT_LO = vst ======================= Files, Options and Parameters ======================= VHDL file = digicoderg0.vbe output file = digicoderg0sc.vst Parameter file = area.lax Mode = Mapping standard cell Optimization mode = 100% area optimization Optimization level = 5 =============================================================================== Compiling 'digicoderg0' ... Running Standard Cell Mapping ============================= INITIAL COST ================================== Total number of literals = 120 Number of reduced literals = 85 Number of latches = 6 Maximum logical depth = 11 Maximum delay = 5.000 =============================================================================== Compiling library '/usr1/projects/gnu/alliance-4.0.6/archi/Solaris/cells/sxlib' Generating Expert System ... Cell 'fulladder_x2' Unused Cell 'fulladder_x4' Unused Cell 'halfadder_x2' Unused Cell 'halfadder_x4' Unused Cell 'mx2_x2' Unused Cell 'mx2_x4' Unused Cell 'mx3_x2' Unused Segmentation Fault make: *** [digicoderg0sc.vst] Error 139 [15] Wilfried > Will be great, when you can help, making the tutorials working. Best thanks in advance Wilfried Tenten 2. using synth -- Mit freundlichen Gruessen / with my best regards =================================================================== Dr. Wilfried Tenten Buero/Office: [49] (7121)35-2986 Robert Bosch GmbH FAX: [49] (7121)35-1746 Dept. K8/EIS2 D-72762 Reutlingen Internet: wilfried.tenten@de.bosch.com Germany K8/EIS (Intranet): http://www.rt.bosch.de/K8/EL1/EIS/Welcome.htm OPTIMISTIC: http://www.imse.cnm.es/esd-msd/PROJECTS/OPTIMISTIC/abstract1.html

 



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