Hi Stefan, It's a bug, C4map doesn't work properly. You'd better use scmap for a Standard Cell Mapping. Hope this help, regards, Ludo. > Hi all, > > I have a question about the alliance CAD system, I find it very powerfull, > however I have a problem (I hope that it is not a boring or trivial > question or even a VHDL coding error... I am not yet a vhdl expert as you > can see!!...) > > I am trying out the c4map program on a very simple example, see the > annexed code hereafter (example.vbe): > > -- -------------------------- > -- Entity Declaration > ENTITY example IS > PORT ( > a : in bit; > b : in bit; > y : out bit); > END example; > > -- Architecture Declaration > ARCHITECTURE aa OF example IS > BEGIN > y <= a or b; > END; > -- --------------------------- > > > I was trying then to run c4map, to map the vbe file to a cmos description, > using the following "param.lax" parameter file: > > #N{3} > #P{3} > > The RDS_TECHNO_NAME variable is set to prol10_8.rds, in the alliance/share/etc dir. > the ELP_TECHNO_NAME is set to prol10.elp > > Then I ran the program: > c4map example zzz param > > the result is shown here: > > @@ @ @ @@ > @@ @ @ @@ @@@ @@ @@@ @@@@ @@@ @@@ > @@ @ @@ @@@ @@ @@ @@ @ @@@ @@ > @@ @ @@ @@ @@ @@ @@ @@ @@ @@ > @@ @@ @@ @@ @@ @@ @@@@@ @@ @@ > @@ @@@@@@@@@ @@ @@ @@ @@ @@ @@ @@ > @@ @ @@ @@ @@ @@ @@ @@ @@ @@ > @@ @@ @@ @@ @@ @@ @@ @@@ @@@ @@ > @@@@ @@@@ @@@@ @@@ @@@ @@@@ @@ @@ @@@ > @@ > @@@@ > > Mapping CCCC > > Alliance CAD System 4.0.6, c4map 4.0.9 [1999/11/09] > Copyright (c) 1990-2000, ASIM/LIP6/UPMC > E-mail support: alliance-support@asim.lip6.fr > > ================================ Environment ================================ > MBK_WORK_LIB = . > MBK_CATA_LIB = ./cellsC4/ > MBK_C4_LIB = ./cellsC4/ > MBK_OUT_PH = ap > MBK_OUT_LO = vst > ======================= Files, Options and Parameters ======================= > VHDL file = example.vbe > output file = zzz.vst > Parameter file = param.lax > Mode = Mapping with compiler cells C4 > Optimization mode = 100% area optimization > Optimization level = 0 > Number of serial transistors on graph P = 3 > Number of serial transistors on graph N = 3 > =============================================================================== > > Compiling 'example' ... > Running Mapping with C4 > ============================= INITIAL COST ================================== > Total number of literals = 2 > Number of reduced literals = 2 > Number of latches = 0 > Maximum logical depth = 1 > Maximum delay = 0.500 > =============================================================================== > Decomposing in feasible functions... > ........ > Generating CMOS Cells in './cellsC4/'... > C4 compilation : > -- or2 > caracLofig of or2 (1) elp=/usr/local/alliance/archi/Linux/etc/prol10.elp > *** mbk error *** : getcapa() impossible. > No rc data on signal 18. > > *********************************^^^^^ > ERROR!!!??? > > After this error I mofified line 17 of the source .vbe file from: > y <= a or b; > to: > y <= not a; > > I ran again the program (after deleting the content of the cellsC4 directory) > everything goes well: > ... > ... > > @@ @ @@ @@ @@ @@ @@ @@ @@ @@ > @@ @@ @@ @@ @@ @@ @@ @@@ @@@ @@ > @@@@ @@@@ @@@@ @@@ @@@ @@@@ @@ @@ @@@ > @@ > @@@@ > > Mapping CCCC > > Alliance CAD System 4.0.6, c4map 4.0.9 [1999/11/09] > Copyright (c) 1990-2000, ASIM/LIP6/UPMC > E-mail support: alliance-support@asim.lip6.fr > > ================================ Environment ================================ > MBK_WORK_LIB = . > MBK_CATA_LIB = ./cellsC4/ > MBK_C4_LIB = ./cellsC4/ > MBK_OUT_PH = ap > MBK_OUT_LO = vst > ======================= Files, Options and Parameters ======================= > VHDL file = example.vbe > output file = zzz.vst > Parameter file = param.lax > Mode = Mapping with compiler cells C4 > Optimization mode = 100% area optimization > Optimization level = 0 > Number of serial transistors on graph P = 3 > Number of serial transistors on graph N = 3 > =============================================================================== > > Compiling 'example' ... > Running Mapping with C4 > ============================= INITIAL COST ================================== > Total number of literals = 1 > Number of reduced literals = 1 > Number of latches = 0 > Maximum logical depth = 0 > Maximum delay = 0.000 > =============================================================================== > Decomposing in feasible functions... > ........ > Generating CMOS Cells in './cellsC4/'... > > ============================== FINAL COST =================================== > Number of cells used = 1 > Number of gates used = 1 > Number of inverters = 1 > Number of grids = 504 > Depth max. (gates) = 1 > (eq. neg. gates) = 1 > =============================================================================== > MBK Driving './zzz.vst'... > > > Why this? > The same thing happens on a Solaris workstation and on my linux box at home... > Perhaps some information is missing in the technology files... > or there is some configuration/environment error... > I have read FAQs and documentation, but I can't solve the problem... > > Can someone help me? > > Thank you very much for the attention, (_) ___ Ludovic JACOMME _ _ ( ) ( ) ( ) ( 6 ) Laboratoire LIP6, Equipe ASIM ( ) (_) ( _ ) Couloir 55-65, 2eme etage, ( )___ ( ) Universite P. et M. Curie (P6) (_____) (_) 4 place Jussieu, 75252 Paris Cedex 05 Tel: (33) 01.44.27.54.15 Fax: (33) 01.44.27.72.80 ICQ: 62526530 mailto: Ludovic.Jacomme@asim.lip6.fr http: //asim.lip6.fr/~ludo