A reply for Question #4: There is always a critical path in a circuit, you can't remove it because there is always a bound time somewhere in the circuit. Anyway, you can minimize the time by inserting buffers or changing cells power ( loon is a tool which do that). GIIE wrote: > Hi there, > > Merry Christmas and a happy new year. > > Just a couple of questions: > > QUESTION#1: > With regards to the email reply: "Re-How can I submit > enhancements to SCR" from which I quote (below): > "I hope you won't be too much disapointed if I tell you that we don't > use scr anymore. Actually, we are using two new tools for Placement > and routing which are ocp and ocr............" what do I do about my > scr and how do I compile - considering I'm running Alliance on Windows > not linux? And can I still use SCR for the mean time? > > QUESTION#2: > How do I correct errors I encounter during the s2r > conversion. The ff are the last few lines of my output: > --> post-treating model sff1_x4 > rectangle merging : > --> post-treating model rowend_x0 > rectangle merging : > --> post-treating model o2_x2 > rectangle merging : > --> post-treating model na3_x1 > rectangle merging : > --> post-treating model addacore1 > ! ; ring flattenning : > rectangle merging : > --> post-treating model addchip > ring flattenning : > rectangle merging : > o replacing black boxes > --> replace cell padreal > cif109: Layer unknown, line 11 > > I suppose that the last line above is an error somewhere. What is to > be done. > > QUESTION#3 > Another error: > I was trying to get around the errors I get whenever I invoke the RING > instruction. After description of pads and core using the PDL, I used > the genlib tool and to get a 'xverchip.vst' file. I then wrote a > (.rin) file to describe the position of pads etc... Upon initiating > the RING instruction, I recieved this all-new error: > > $ ring xverchip xverchip > > @@@@@@@ @ @@@@ @ > @@ @@ @@@ @@ @@ > &! nbsp; @@ @@ @ @@ @ > @@ @@ @@@ @@@ @@ > @@ @@ @@@@ @@@ @ @@ > @@@@@ @@ @@ @@ @@ @@@@@ > ! @@ @@ @@ @@ @@ @@ @ @@ > @@ @@ @@ @@ @@ @@ @ @@ > @@ @@ @@ @@ @@ @@ @@ > @@ @@ @@ @@ @@ @@ @@ > &nb! sp; @@@@@ @@@ @@@@@@ @@@@ @@@@ @@@@ > > PAD ring router > > Alliance CAD System 4.5.0, ring 2.11 > Copyright (c) 1991-2001, ASIM/LIP6/UPMC > E-mail support: allianc! e-support@asim.lip6.fr > > o reading netlists, layout views of core and pads. > o reading file of parameters, including the placements of > pads. > o making equipotential list. > o making the first placement of pads. > o filling data internal structures. > o reading the connectors positions of the core. > o computing the best placement of the pads. > o reading the connectors positions of the pads. > o routing deportation of connectors. > No space hasn't been found for the connector <t> of the instance <b0>. > > I re-run the whole thing again and I ge! t the same error. Is there a > way to increase the layout space so it can find somewhere to place > connector 't'. > > QUESTION#4 > With regards to the XSCH tool this time. Using the boog tool, (.vst) > and (.xsc) files are generated. Viewing the schematic, I noticed the > critical paths. Is there a way to correct my design to remove the > critical paths. I already optimized the behavioral description using > boom. > How can critical paths be removed? > > > > Thanks > Giie > > > ----------------------------------------------------------------------- > Do You Yahoo!? > Send your FREE holiday greetings online at Yahoo! Greetings.