NIRANJAN PRABHU wrote: Hello, I have attached a VHDL code below. I tried compiling this behavioural model but could not. I just want to know if the below can be done? If yes, the method. x(1) <= (( a(1) AND b(0) ) XOR ( a(0) AND b(1) )); is a behavioural vhdl view u1 : mul PORT MAP (a,b,out); is a structural vhdl view ... you'll have to split in two files : .vbe and .vst. Alliance .vbe is for behavioural vhdl view Alliance .vst is for structural vhdl view Please look at amd2901 tutorial. -- Sincerely, Olivier. ==================================================================== Olivier SIROL Alliance Team ASIM/LIP6/UPMC Coul. 55-65, 2e etg, Bur. 213 75252 Paris Cedex 05 mailto:Olivier.Sirol@lip6.fr Tel: (33/0) 1.44.27.74.78 http://asim.lip6.fr/~czo/ Fax: (33/0) 1.44.27.72.80