The specified assembly language can be used undifferently for both CISC (micro-programmed) and RISC (pipeline) version of DLX.
The command line syntax is:
dlx_asm [-p] [-size n] <assembly_file> <result_vhdl_file>
For the RISC version option -p must be specified.
The size of the result ROM can be specified using the -size
option, where n
is the number of instructions in the ROM.
By default, dlx_asm produces a ROM of 64 instructions.
<label> <opcode> <operands>
label
is a string used to tag a specific statement or a portion of
the program. A label
must be followed by :
(colon) if
there is a newline between the label
and the opcode
.
opcode
is a string representing either an effective instruction or
a pseudo instruction.
An effective instruction is either an instruction from the DLX's instruction set or a macro-instruction. The assembler expands a macro-instruction into a set of DLX's instructions.
operands
is a list of arguments. Depending on the opcode
,
an assmebly statement needs from 0 up to 3 arguments. Arguments must be seperated by
,
(comma).
A comment begins with ;
(semicolon) and extends until the end of the
line.
add Rd, Rs, Rt
|
add register to register (signed arithmetic).
Rd <- Rs + Rt
|
addu Rd, Rs, Rt
|
(pipeline architecture) add register to register (unsigned arithmetic).
Rd <- Rs + Rt
|
sub Rd, Rs, Rt
|
subtract register from register (signed arithmetic).
Rd <- Rs - Rt
|
subu Rd, Rs, Rt
|
(pipeline architecture) subtract register from register (unsigned arithmetic).
Rd <- Rs - Rt
|
and Rd, Rs, Rt
|
perform logical bitwise and between two registers:
Rd <- Rs and Rt
|
or Rd, Rs, Rt
|
perform logical bitwise or between two registers:
Rd <- Rs or Rt
|
xor Rd, Rs, Rt
|
perform logical bitwise exclusive or between two registers:
Rd <- Rs xor Rt
|
addi Rd, Rs, I
|
add immediate to register (signed arithmetic - 16 bits signed immediate extended
to 32 bits).
Rd <- Rs + I
|
addui Rd, Rs, I
|
(pipeline architecture) add immediate to register (unsigned arithmetic - 16
bits unsigned immediate extended to 32 bits).
Rd <- Rs + I
|
subi Rd, Rs, I
|
subtract immediate from register (signed arithmetic - 16 bits signed immediate
extended to 32 bits).
Rd <- Rs - I
|
subui Rd, Rs, I
|
(pipeline architecture) subtract immediate from register (unsigned arithmetic
- 16 bits unsigned immediate extended to 32 bits).
Rd <- Rs - I
|
andi Rd, Rs, I
|
perform logical bitwise and between immediate and register (16 bits unsigned
immediate extended to 32 bits):
Rd <- Rs and I
|
ori Rd, Rs, I
|
perform logical bitwise or between immediate and register (16 bits unsigned
immediate extended to 32 bits):
Rd <- Rs or I
|
xori Rd, Rs, I
|
perform logical bitwise exclusive or between immediate and register (16 bits
unsigned immediate extended to 32 bits):
Rd <- Rs xor I
|
sll Rd, Rs, Rt
|
shift left register (only the 5 LSb of Rt are significant):
Rd <- Rs << Rt
|
srl Rd, Rs, Rt
|
shift right register (logic - only the 5 LSb of Rt are significant):
Rd <- Rs << Rt
|
sra Rd, Rs, Rt
|
shift right register (arithmetic - only the 5 LSb of Rt are significant):
Rd <- Rs << Rt
|
slli Rd, Rs, I
|
shift left register (5 bits unsigned immediate):
Rd <- Rs << I
|
srli Rd, Rs, I
|
shift right register (logic - 5 bits unsigned immediate):
Rd <- Rs << I
|
srai Rd, Rs, I
|
shift right register (arithmetic - 5 bits unsigned immediate):
Rd <- Rs << I
|
lhi Rd, I
|
load high order bits of register (16 bits immediate completed with 16 zeros
at last significant bits):
Rd <- I
|
seq Rd, Rs, Rt
|
set register if equal zero:
Rd <- 1 if (Rs = Rt) else 0
|
sne Rd, Rs, Rt
|
set register if non equal zero:
Rd <- 1 if (Rs != Rt) else 0
|
sge Rd, Rs, Rt
|
set register if greater than or equal zero:
Rd <- 1 if (Rs >= Rt) else 0
|
sle Rd, Rs, Rt
|
set register if less than or equal zero:
Rd <- 1 if (Rs <= Rt) else 0
|
sleu Rd, Rs, Rt
|
(pipeline architecture) set register if less than or equal zero (unsigned):
Rd <- 1 if (Rs <= Rt) else 0
|
sgt Rd, Rs, Rt
|
set register if greater than:
Rd <- 1 if (Rs > Rt) else 0
|
slt Rd, Rs, Rt
|
set register if less than:
Rd <- 1 if (Rs < Rt) else 0
|
seqi Rd, Rs, I
|
set register if equal zero (16 bits signed immediate extended to 32 bits):
Rd <- 1 if (Rs = I) else 0
|
snei Rd, Rs, I
|
set register if not equal zero (16 bits signed immediate extended to 32 bits):
Rd <- 1 if (Rs != I) else 0
|
sgei Rd, Rs, I
|
set register if greater than or equal zero (16 bits signed immediate extended
to 32 bits):
Rd <- 1 if (Rs >= I) else 0
|
slei Rd, Rs, I
|
set register if less than or equal zero (16 bits signed immediate extended to
32 bits):
Rd <- 1 if (Rs <= I) else 0
|
sgti Rd, Rs, I
|
set register if greater than (16 bits signed immediate extended to 32 bits):
Rd <- 1 if (Rs > I) else 0
|
slti Rd, Rs, I
|
set register if less than (16 bits signed immediate extended to 32 bits):
Rd <- 1 if (Rs < I) else 0
|
sw I(Rs), Rt
|
store register (word) into external storage (16 bits signed immediate extended
to 32 bits):
Storage (Rs + I) <- Rt
|
sh I(Rs), Rt
|
(pipeline architecture) store half-word (2 last significant bytes) of register
into external storage (16 bits signed immediate extended to 32 bits):
Storage (Rs + I) <- Rt
|
sb I(Rs), Rt
|
store the last significant byte of register into external storage (16 bits
signed immediate extended to 32 bits):
Storage (Rs + I) <- Rt
|
lw Rd, I(Rs)
|
load a word from external storage into register (16 bits signed immediate
extended to 32 bits):
Rd <- Storage (Rs + I)
|
lh Rd, I(Rs)
|
(pipeline architecture) load a signed half-word (2 bytes) from external storage
into register (16 bits signed immediate extended to 32 bits - the signed
half-word read from external storage is extended to 32 bits):
Rd <- Storage (Rs + I)
|
lhu Rd, I(Rs)
|
(pipeline architecture) load an unsigned half-word (2 bytes) from external
storage into register (16 bits signed immediate extended to 32 bits - the
unsigned half-word read from external storage is extended to 32 bits):
Rd <- Storage (Rs + I)
|
lb Rd, I(Rs)
|
(pipeline architecture) load a signed single byte from external storage into
register (16 bits signed immediate extended to 32 bits - the signed byte read
from external storage is extended to 32 bits):
Rd <- Storage (Rs + I)
|
lbu Rd, I(Rs)
|
load an unsigned single byte from external storage into register (16 bits
signed immediate extended to 32 bits - the unsigned byte read from external
storage is extended to 32 bits):
Rd <- Storage (Rs + I)
|
jr Rs
|
jump register:
PC <- Rs
|
jalr Rs
|
jump and link register:
PC <- Rs R31 <- PC + 4
|
movs2i Rd, S
|
move special register (S may be IAR, SR or TVR) into integer register
(privileged instruction):
Rd <- S
|
movi2s S, Rs
|
move integer register into special register (S may be IAR, SR or TVR)
(privileged instruction):
S <- Rs
|
beqz Rs, label
|
branch if equal zero:
PC <- label if (Rs = 0)
|
bnez Rs, label
|
branch if not equal zero:
PC <- label if (Rs != 0)
|
j label
|
jump:
PC <- label
|
jal label
|
jump and link:
PC <- label
|
rfe
|
return from interrupt (privileged instruction):
|
trap I
|
software interrupt (26 bits immediate: trap number)
|
Macro-instructions are the following:
nop
|
no operation
|
loadi Rd, I
|
load immediate into register (32 bits immediate):
Rd <- I
|
EQU I
|
assign the value of an immediate to a label .
|
ORG address
|
set the address (of the first statement) of the program to the location defined by the immediate (32 bits). |
START label
|
marks the first statement of the program to be executed. |
END
|
marks the end of the program. |
;
(semicolon) and extends until the end of
the line.
Immediate values can be expressed using decimal, binary, octal or hexadecimal representations:
-235 decimal value B"01011" binary value 0"376" octal value X"0f72" hexadecimal value
A static expression can be used instead of an immediate. The following operations are allowed inside expressions :
+ arithmetic addition - arithmetic subtraction * arithmetic multiplication >> shift arithmetic right << shift logical left
dlx_asm -p prog romu
![]() Université Pierre et Marie Curie - CNRS |
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