Hello again sir, I am designing a register file of 32 registers of 32 bits each. All have a common input 'data_in'. First, I wrote the behavioral description of a 32 bit register, simulated it etc - there were no errors. Next, I cascaded it in a structural description for the 32 registers. I connected all the outputs of the individual registers together because I wanted a bus since the register block would have read and write pin. Checking for syntax errors : no problem. I wrote the pattern file, and then I recieve the following errors upon simulation: Error 114: multiple driver on unguarded signal `reg_dataout 0` Error 114: multiple driver on unguarded signal `reg_dataout 1` Error 114: multiple driver on unguarded signal `reg_dataout 2` Error 114: multiple driver on unguarded signal `reg_dataout 3` Error 114: multiple driver on unguarded signal `reg_dataout 4` Error 114: multiple driver on unguarded signal `reg_dataout 5` ****( this continues for until reg_dataout 31) I sense the errors are with the declaration of "reg_dataout" in the structural description. I declared it as "Reg_Dataout : out bit_vector(31 downto 0) ". Changing this to "Reg_Dataout : out mux_vector(31 downto 0) Bus" results in even more errors. Looking at the documentation(ASIM website) for the allowed structural subset, it was not stated whether the "mux_vector..." can be used in a structural description. Q1: Is the statement "Reg_Dataout : out mux_vector(31 downto 0) Bus" acceptable in a structural description? Q2. With the explanation of my given circuit, how can I declare a bus for register file output "Reg_dataout" so that I could use the "read" pins in my design to select which of the 32 register content I want on placed the bus. Thanks, Giie --------------------------------- Do You Yahoo!? Yahoo! Auctions Great stuff seeking new owners! Bid now!