alliance-support '2000
Re: Vasy question


Ludovic JACOMME (Ludovic.JACOMME@asim.lip6.fr)
Tue, 21 Mar 2000 17:16:09 +0100

Hi Stefan, VASY simulates all your description during one VHDL delta-cycle and according to the LRM : The input A is set to 0 (the most left value of its type) when VASY executes the process, then the expression A - 1 is equal to -1. Then VASY tries to propagate this new value to the output B. But B can takes only integer values from 0 to 8. The value -1 is not in this interval and the simulation stops with an error (overflow). I will soon modify VASY in order to avoid this type of behavior. For the moment you just have to modify your description : library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; entity adder is port( A : in INTEGER range 0 to 8 := 1; -- -- ^^^^^ -- B : out INTEGER range 0 to 8); end adder; architecture rtl_1 of adder is begin process( A ) begin B<=A-1; end process; end rtl_1; Hope this help, (_) ___ Ludovic JACOMME _ _ ( ) ( ) ( ) ( 6 ) Laboratoire LIP6, Equipe ASIM ( ) (_) ( _ ) Couloir 55-65, 2eme etage, ( )___ ( ) Universite P. et M. Curie (P6) (_____) (_) 4 place Jussieu, 75252 Paris Cedex 05 Tel: (33) 01.44.27.54.15 Fax: (33) 01.44.27.72.80 ICQ: 62526530 mailto: Ludovic.Jacomme@asim.lip6.fr http: //asim.lip6.fr/~ludo

 



Alliance Web Site © 1997, 2002 ASIM/LIP6/UPMC, page maintained by Czo [Olivier Sirol] , last updated on 22 March 2001.