alliance-users '1998
Re: Urgent Help


Czo [Olivier Sirol] (Olivier.Sirol@asim.lip6.fr)
Mon, 30 Nov 1998 15:41:00 +0100

"Luis A. Caceres" wrote: > > Hi all, > > I am beginner with VHDL-Alliance, and have some problems for to invoke > custom circuit in another circuit. > > I have described one full adder (myFullAdder.vbe = two output's ). > Now I need to describe one circuit that invoke my full adder, > as one component. > > The question is: how can I get that alliance to recognize my circuit? > How can I to define my circuit ? and later call it as one component? > > Example: > entity circuit is > port ( A, B,C: in BIT; > X,Y: out BIT); > end; > > architecture STRUCTURE of circuit is > component myFullAdder <----------- This is the problem: > port (A,B,C: in BIT; myFullAdder > is not Scell, > X,Y: out BIT); How I get > that Alliance recognize it? > end component; > > begin > ...structural description... > end; > > Thank in advance by your help!!!!! I am just forwarding the answer given by Ludovic... Forwarded message: > From ludo Wed Oct 14 17:29:20 1998 > Subject: Re: Urgent Help > To: hakimus@univalle.edu.co (Luis A. Caceres) > Date: Wed, 14 Oct 1998 17:29:20 +0200 (MET DST) > In-Reply-To: <3624C014.D877CE82@univalle.edu.co> from "Luis A. Caceres" at Oct 14, 98 10:15:33 am > X-Mailer: ELM [version 2.4 PL25 PGP8] > MIME-Version: 1.0 > Content-Type: text/plain; charset=US-ASCII > Content-Transfer-Encoding: 7bit > Content-Length: 1986 > > > > > Hi all, > > > > I am beginner with VHDL-Alliance, and have some problems for to invoke > > custom circuit in another circuit. > > > > I have described one full adder (myFullAdder.vbe = two output's ). > > Now I need to describe one circuit that invoke my full adder, > > as one component. > > > > The question is: how can I get that alliance to recognize my circuit? > > How can I to define my circuit ? and later call it as one component? > > > > Example: > > entity circuit is > > port ( A, B,C: in BIT; > > X,Y: out BIT); > > end; > > > > architecture STRUCTURE of circuit is > > component myFullAdder <----------- This is the problem: > > port (A,B,C: in BIT; myFullAdder > > is not Scell, > > X,Y: out BIT); How I get > > that Alliance recognize it? > > end component; > > > > begin > > ...structural description... > > end; > > > > Thank in advance by your help!!!!! > > > > Luis A. Caceres. > > > > PD: Please help me, I not have another resource. > > > > > Hi ! > > I suggest you to have a look on the tutorial of the addaccu. > If you want to use your component myFullAdder in the structural view > of your circuit you have to write the behaviour of myFullAdder in a file > myfulladder.vbe. > I you want a physical view of your circuit you need to create a structural > view of your cell myFullAdder (with bop and scmap). > > Good luck Ludo. > > (_) ___ Ludovic JACOMME > _ _ ( ) > ( ) ( ) ( 6 ) Laboratoire LIP6, Equipe ASIM > ( ) (_) ( _ ) Couloir 55-65, 2eme etage, > ( )___ ( ) Universite P. et M. Curie (P6) > (_____) (_) 4 place Jussieu, 75252 Paris Cedex 05 > > Tel: (33) 01.44.27.54.15 > Fax: (33) 01.44.27.72.80 > > e-mail: Ludovic.Jacomme@asim.lip6.fr > > Thanks for your interest in Alliance. Sincerely, Olivier Sirol. ==================================================================== Olivier SIROL Alliance Team ASIM/LIP6/UPMC Coul. 55-65, 2e etg, Bur. 204 75252 Paris Cedex 05 mailto:alliance-support@asim.lip6.fr Tel: +33 1 44 27 53 24 http://asim.lip6.fr/alliance/ Fax: +33 1 44 27 72 80 ====================================================================

 



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