- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - This message is sent to the hundreds of members of the "alliance@masi.ibp.fr" mailing-list all through the world. Please don't bother them with administrative requests such as 'help', 'subscribe', 'unsubscribe'... Instead, use the adress "alliance-request@masi.ibp.fr" for such administrative requests. If you feel the absolute need to talk to an human, use the adress 'cao-vlsi@masi.ibp.fr'. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Dear Sirs, I 've written you again asking questions concerning Alliance and I thank you for your informations. I have several more questions to ask you: 1) I am using the time analysis tool Tas. First of all I do not understand what do you mean by the terms input_commutation, output_commutation and delay resistance slope that I've read in the man pages ? I have a segment from a .ttv file below, can you explain me on it? How can I know which internal signal is c.mbk_sig2 ? T X b c ( (* (DD 1274 2.32 382)) # DOWN(b) = UP(c.mbk_sig2), Tp=880 pS # UP(c.mbk_sig2) = DOWN(c), Tp=394 pS (* (UU 1111 2.09 316)) # UP(b) = DOWN(c.mbk_sig2), Tp=586 pS # DOWN(c.mbk_sig2) = UP(c), Tp=525 pS ); I ran also into some troubles using TaS. The first one was that after finishing the analysis of a circuit and I suppose it was ready to write the results, it crashed reporting a segmentetion fault. The circuit wasn't big or complex and I succesfully managed to analyze some independant modules of it earlier. The second problem was that, while analyzing a circuit (with a lot of CMOS switches that I had defined), it crashed in functional analysis reporting: "mbk error, fatal mbkalloc error, not enough memory ". My computer is a Pentium with 32Mb Ram running Linux 2.0.0 2) I am using asimut and .pat files to simulate my designs. I am wondering, is it possible somehow not to give predicted values for the outputs and just have asimut to write down the evaluated outputs? Are there any don't cares for the inputs (as * for the outputs)? 3) In the scr man pages I've read that you can use a user defined placement file. Could you give me more informations about that? What's the format? What can you do? I would also prefer not all leaf cells to be shown in a .ap file. I see that the -c option gives me a more hierarhical view. If I write "scr -r -p -c design.vst", only the cells that I use in the top .vst file (design.vst) will appear? What if I want for some cells to be shown in greater detail? Should I have to change the .vst file? 4) I've noticed that there are two kinds of library cells (with fanout 1 and 2). Can I use a fanout 2 gate to drive 4 other gates? Is there going to be another effect except the increased delay? (due to increased output capacitance). NOTE: I can't use for the moment the genlib tool, or any other tool that uses the C functions Loins, Logon etc.. due to problems with the library formats. Thank you again for your attention. Thanassis Boulis VLSI lab, Technical University of Crete Please reply to: siaper@ced.tuc.gr including the word 'Boulis' in the text or subject AND to: vlsi@tarra.ced.tuc.gr -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - END-OF-MAIL