alliance-support '01
Alliance's VHDL Subset


Shehryar.Shaheen (Shehryar.Shaheen@ul.ie)
Wed, 05 Sep 2001 19:50:34 +0100

Dear Sir/Madam I am a student at the University of Limerick & I am interested in using the tool for my project. One question that I have is that it's mentioned on your site that "The alliance VHDL subset does not support The process statement in VHDL" but also for modeling statemachines an example has been given (on the web site) In which the process statement has been used. What I want to know is that if I use the alliance tool can I use the process statement for modeling sequential logic or not ? If the tool does not support the process statement then this would be a serious limitation when modeling sequential logic. Regards Shehryar For example can I use the following piece of code .......... .......... - some statements .......... Signal temp : unsigned(7 downto 0); Seq : process (clock,reset) Begin If (reset = '1' ) Temp <= (others => '0'); Elsif(clock='1' and clock'event) ............... ................... ................... - some statements

 



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