Table of Contents

Name

genlib - Procedural design language based upon C, along with its compiler

Origin

This software belongs to the ALLIANCE CAD system from the CAO-VLSI team at ASIM/LIP6/UPMC laboratory.
LIP6/ASIM
University P. et M. Curie 4, place Jussieu 75252 PARIS Cedex 05 FRANCE
Fax : {33/0} 1.44.27.62.86
E-mail support : alliance-support@asim.lip6.fr

Description

genlib is a set of C functions dedicated to procedural generation purposes. From a user point of view, genlib is a circuit's description language that allows standard C programming flow control, variable use, and specialized functions in order to handle vlsi objects. Based upon the Alliance mbk data structures, the genlib language gives the user the ability to describe both netlist and layout views, thus allowing both standard cell and full custom approachs.

Netlist capture :
- it is a hierachical structural description of a circuit in terms of connectors (I/Os), signals (nets), and instances. The function calls used to handle the netlist view are DEF_LOFIG(3) SAVE_LOFIG(3) LOINS(3) LOCON(3) LOSIG(3) FLATTEN_LOFIG(3) Some facilities, in order to create vectors are also available : BUS(3) ELM(3)

Standard cell placement
The following functions allows to define a placement file for a standard cell design. This file can be used by the standard cell router scr(1) . DEF_PHSC(3)
SAVE_PHSC(3)
SC_PLACE(3)
SC_RIGHT(3)
SC_TOP(3)
SC_LEFT(3)
SC_BOTTOM(3)

Full custom symbolic layout
Those functions are dedicated to optimized full custom procedural layout. In order to provide some process independance, Alliance uses a symbolic layout approach (fixed grid without compaction.) The symbolic objects are segments (wires), vias (contacts), connectors (I/Os), references and instances. For more informations, see phseg(1) , phvia(1) , phcon(1) , phref(1) , phins(1) , and alc(1) . DEF_PHFIG(3)
SAVE_PHFIG(3)
DEF_AB(3)
DEF_PHINS(3)
PHCON(3)
COPY_UP_CON(3)
COPY_UP_CON_FACE(3) COPY_UP_ALL_CON(3) PHSEG(3)
COPY_UP_SEG(3)
THRU_H(3)
THRU_V(3)
THRU_CON_H(3)
THRU_CON_V(3)
WIRE1(3)
WIRE2(3)
WIRE3(3)
PHVIA(3)
PLACE(3)
PLACE_RIGHT(3)
PLACE_TOP(3)
PLACE_LEFT(3)
PLACE_BOTTOM(3)
PLACE_ON(3)
PHREF(3)
COPY_UP_REF(3)
COPY_UP_ALL_REF(3) PLACE_VIA_REF(3)
PLACE_CON_REF(3)
PLACE_SEG_REF(3)
FLATTEN_PHFIG(3)
GET_REF_X(3)
GET_REF_Y(3)
GET_CON_X(3)
GET_CON_Y(3)
HEIGHT(3)
WIDTH(3)

In order to have information about each of these functions, use the online documentation with man(1) , as in ``man function-name''.

It is strongly recommended to read some books on C programming, in order to take full advantage of the C flow control possibilities, as it may greatly reduce the size of a genlib source code.

Environment Variables

the variables are : name
default value
MBK_IN_LO(1)
al
MBK_OUT_LO(1)
al
MBK_IN_PH(1)
ap
MBK_OUT_PH(1)
ap
MBK_CATA_LIB(1)
.
MBK_WORK_LIB(1)
.
MBK_CATAL_NAME(1)
CATAL

see the corresponding manual pages for further informations. In order to compile and execute a genlib file, one has to call genlib with one argument, that is the genlib source file. The source file must have a .c extension, but the extension should not be mentionned on the command line.

The names used in genlib, as arguments to genlib functions, should be alphanumerical, including the underscore. They also are not case sensitive, so VDD is equivalent to vdd. Vectorized connectors or signal can be declareds using the [n:m] construct.

Options

Two options can alter the behavior of genlib :

-v
displays everything that is to be done during the compilation and execution process: verbose mode.
-k
keeps the executable along with the compilation Makefile after completion.

Examples

genlib -v amd2901
Compiles and runs a genlib source file called amd2901.c

See Also

mbk(1) , alc(1) , scr(1) , bgd(1) , bsg(1) , grog(1) , rsa(1) .

Diagnostics

Compilation aborted
This indicates either a C syntaxic error, most likely, or a misinstallation of the mbk package of the Alliance CAD system, if the error is cannot find file genlib.h.
Link aborted
This indicates a misinstallation of the mbk package of the Alliance CAD system, see your system administrator for details.

Many errors may occur while executing the source file, so refer to the proper genlib function manual for more.

Bug Report

This tool is under development at the ASIM/LIP6/UPMC laboratory, cao-vlsi research team.
We need your feedbak to improve documentation and tools. If you find bugs, please fill-in the form at http://asim.lip6.fr/alliance/support/bug-report/ Thanks for doing this.


Table of Contents

 



Alliance Web Site © 1997, 2002 ASIM/LIP6/UPMC, page maintained by Czo [Olivier Sirol] , last updated on 26 May 2000.