alliance-support '01
Re-Re: Flipflop design


GIIE (beloved_j@yahoo.com)
Mon, 12 Nov 2001 17:49:45 -0800 (PST)

Hello sir Francois, Thanks for your help on the flipflop issue. I modified my code and simulated it, however I dont know if the result is correct, since I was expecting the output to toggle between 0 and 1 just like a flip-flop. Here it is: -- vv c k q -- ds l -- ds o -- c -- k < 0 ps> pat_0 : 10 1 0 ?u ; < 1 ps> pat_1 : 10 0 0 ?u ; < 2 ps> pat_2 : 10 1 1 ?1 ; < 3 ps> pat_3 : 10 0 1 ?1 ; < 4 ps> pat_4 : 10 1 0 ?0 ; < 5 ps> pat_5 : 10 0 0 ?0 ; < 6 ps> pat_6 : 10 1 1 ?1 ; < 7 ps> pat_7 : 10 0 1 ?1 ; Is this kind of output correct for a jk flipflop? Another question sir, I tried connecting the ff's together to emulate a 4-bit counter, however I get an error "Illegal connection on signal......." when I try to simulate the structural description. The identified error is with regards to for example: when I connect the Q output of ff#1 to the clock input of ff#2 and the Q output of ff#2 to the clock input of ff#3 so on etc. What can I do about this? Thanks sir --------------------------------- Do You Yahoo!? Find a job, post your resume on Yahoo! Careers.

 



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