alliance-support '01
Re: Fwd: Re: GENLIB -HELP


Christophe Alexandre (Christophe.Alexandre@asim.lip6.fr)
Wed, 12 Dec 2001 15:32:44 +0100 (CET)

On Wed, 12 Dec 2001, John da Beloved wrote: > > > > "GENLIB_LOINS("core", "core","aa[0:3]", "bb[0:3]", "selsel", "clock", "ss[0:3]","vdd", "vss", 0);" > > > > I suppose the first "core" in the statement above calls the core.c file (pls, am I correct?) No, you're wrong. The first "core" is the model of the instance you're are creating (second "core"). So it's depending on your design hierarchy a .vbe or .vst file. That means you need to create the desing of your core first. > > > > for my design, a similar statement in my halfchip.c file reads: > > "GENLIB_LOINS("core", "halfcore", "xx", "yy", "clock", "sum", "vdd", "vss", 0);" .... (1) > > > > Upon issuing the genlib instruction, I get the error: > > "Generating the Makefile > > Compiling, ... > > Current execution environment > > MBK_CATA_LIB : /usr/local/alliance/archi/Cygwin/cells/padlib > > MBK_WORK_LIB : . > > MBK_IN_LO : vst > > MBK_OUT_LO : vst > > MBK_IN_PH : ap > > MBK_OUT_PH : ap > > MBK_CATAL_NAME : CATAL > > Executing ... > > > > *** mbk error *** can't open file : core.vbe > > Removing tmp files ..." > > Is your core a behavioural or a structural description ? If it's structural (a .vst file) than you have created a core.vst file. Add a . to you MBK_CATA_LIB environment and by the way add the sxlib cells path too because you'll have problem in the future. If it's behavioural than you must have a core.vbe file. In that case you must write a CATAL file with the line: core C and you must have a . in your MBK_CATA_LIB here too. This is to tell the tools to look in the current directory. Christophe Alexandre.

 



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