alliance-support '2000
Re: Illegal concurrent statement


Ludovic JACOMME (Ludovic.JACOMME@asim.lip6.fr)
Tue, 29 Feb 2000 13:42:27 +0100

Hi Pierre, > I tried to compile the following and got this from vasy: > --> Run VHDL Compiler > --> Compile file codegen > Error line 39 : parse error > vbl_bcomp.yac 2736 : Error 18 line 39 :illegal concurrent statement > What's wrong? > > phma In VHDL, if you want to assign a signal S you have to write : S <= Expression; Not : S = Expression; > slideclock: process(clk,slipsync) > begin > if (slipsync'event and not slipsync) then > slipinternal=1; ^^^^^^^^^^^^^^^ > end if; > if (clk'event and slipinternal and not clk) then > slopinternal=1; ^^^^^^^^^^^^^^^ > slipinternal=0; ^^^^^^^^^^^^^^^ > end if; > if (clk'event and slopinternal and not clk) then > slopinternal=0; ^^^^^^^^^^^^^^^ > end if; > slipclk=clk and not slopinternal; ^^^^^^^^^^^^^^^ > end process slideclock; > > count: process(slipclk) > begin > if (slipclk'event and slipclk) then > carries(0)=1; ^^^^^^^^^^^^^^^ > carries(6 downto 1)=carries(5 downto 0) and counter(5 downto 0); ^^^^^^^^^^^^^^^ > counter(6 downto 0)=counter(6 downto 0) xor carries(6 downto 0); ^^^^^^^^^^^^^^^ > chipclk=counter(4); ^^^^^^^^^^^^^^^ > end process count; > end behavior; > Regards, (_) ___ Ludovic JACOMME _ _ ( ) ( ) ( ) ( 6 ) Laboratoire LIP6, Equipe ASIM ( ) (_) ( _ ) Couloir 55-65, 2eme etage, ( )___ ( ) Universite P. et M. Curie (P6) (_____) (_) 4 place Jussieu, 75252 Paris Cedex 05 Tel: (33) 01.44.27.54.15 Fax: (33) 01.44.27.72.80 ICQ: 62526530 mailto: Ludovic.Jacomme@asim.lip6.fr http: //asim.lip6.fr/~ludo

 



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