alliance-support '01
Re: Alliance's VHDL Subset


Ludovic JACOMME (Ludovic.JACOMME@asim.lip6.fr)
Mon, 10 Sep 2001 18:15:59 +0200

Hi, You can use the VASY tool (included in the last Alliance distribution or on my web site asim.lip6.fr/~ludo/alliance/download/) in order to translate your VHDL description to the VHDL Alliance subset (see vasy(1) and vasy(5) man page for more informations about the vasy VHDL subset) Best regards, On Wed, Sep 05, 2001 at 07:50:34PM +0100, Shehryar.Shaheen wrote: > Dear Sir/Madam > I am a student at the University of Limerick & I am > interested in using the tool for my project. > > One question that I have is that it's mentioned on your site that "The > alliance VHDL subset does not support > The process statement in VHDL" but also for modeling statemachines an > example has been given (on the web site) > In which the process statement has been used. > > What I want to know is that if I use the alliance tool can I use the process > statement for modeling sequential logic or not ? > > If the tool does not support the process statement then this would be a > serious limitation when modeling sequential logic. > > Regards > > Shehryar > > For example can I use the following piece of code > > .......... > .......... - some statements > .......... > Signal temp : unsigned(7 downto 0); > > Seq : process (clock,reset) > Begin > If (reset = '1' ) > Temp <= (others => '0'); > Elsif(clock='1' and clock'event) > ............... > ................... > ................... - some statements (_) ___ Ludovic JACOMME _ _ ( ) ( ) ( ) ( 6 ) Laboratoire LIP6, Equipe ASIM ( ) (_) ( _ ) Couloir 65-66, 4eme etage Porte 405, ( )___ ( ) Universite P. et M. Curie (P6) (_____) (_) 4 place Jussieu, 75252 Paris Cedex 05 Tel: (33) 01.44.27.27.06 01.44.27.54.15 Fax: (33) 01.44.27.72.80 ICQ: 62526530 mailto: Ludovic.Jacomme@asim.lip6.fr http: //asim.lip6.fr/~ludo

 



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