.vbe
and in a
.c
file: The behavioural description amd.vbe
is
used for simulation purposes as a proof-of-concept and to prove that the
resulting layout satisfies the specifications whilst the chip.c
file
describes the structure of the Am2901 blocks.
What this means is that there is no need to use a cells' mapper since the fitting
is already done in the structural description (.c
file).
genlib will take as input the chip.c
file and it will create
the description of seven blocks:
ram.vst
: the 16-word by 4-bit dual ported RAM in data sheet's
Figure 1;
accu.vst
: the Q register in data sheet's Figure 1;
alu.vst
: the ALU in data sheet's Figure 1;
muxe.vst
: the associated multiplexers for the ALU in data
sheet's Figure 1;
muxout.vst
: the output multiplexer in data sheet's Figure 1;
heart.vst
: the Am2901's core; and,
chip.vst
: the Am2901' chip.
Figure 1 shows the block diagram for the first six blocks.
![]() |
Figure 1. Block diagram for the Am2901's core. |
Figure 2 shows how the core is interconnected to the outside. Take a look at the smaller blocks; they represent the pads, which provide the interface to the outside. In this circuit, there are 3 classes of pads (pad cells are strongly dependant on the target technology):
pvdde_sp
: provides the Vdd supply for the pads (see man
pvdde_sp
)
pvsse_sp
: provides the Vdd supply for the pads (see man
pvdde_sp
)
pvddi_sp
: provides the Vdd supply for the core (see man
pvddi_sp
)
pvssi_sp
: provides the Vss supply for the core (see man
pvssi_sp
)
pvsseck_sp
: a clock pad (see man pvsseck_sp
)
pck_sp
: a clock buffer (see man pck_sp
)
po_sp
: an output pad (see man po_sp
)
pi_sp
: an input pad (see man pi_sp
)
pot_sp
: a three-state output pad (see man pot_sp
)
piot_sp
: an input/output pad (see man piot_sp
)
To minimize noise within the core, the pads use a different power supply than that in the standard cells (used for the core). Hence, each chip has two power supplies; one for the pads and the other for the core. Should you examine the chip's layout you will notice that it has a series of concentrical rings around the core; these are the tracks for the power supplies and the clock.
![]() |
Figure 2. Block diagram for the Am2901. |
Take a look at the lower right corner of the previous figure. As you can see this particular implementation provides a serial scan interface for testing purposes.
Check the IEEE Computer special issue on System Testing & Reliability:
IEEE Computer, 29(12), November 1996. IEEE Computer Society.
Makefile
you will have an automatic replay of the
addaccu
tutorial. However you will be doing the whole chip design
and verification at once.
To get a more detailed insigth of the methodology you could still use the
Makefile
but now with other targets, not just with the primary one.
The following table is provided as a hint:
Target | Action | Results |
---|---|---|
clean | clean up the directory for tutorial re-run | Minimum required files |
asimut_first | asimut compilation. |
asimut_first
|
asimut_vbe |
the hardware behaviour description amd.vbe is simulated by asimut,
using the test patterns previously generated in pattern.pat .
|
asimut_vbe result_beh.pat
|
chip.vst |
genlib is a procedural design language upon C. Every netlist source files
with a .c extension are compiled by genlib which gives the
corresponding gate netlists ended by .vst extension.
|
accu.vst alu.vst chip.vst heart.vst muxe.vst muxout.vst ram.vst
|
asimut_vst | check the correctness of the generated structural description running the logic simulation. |
asimut_vst result_str.pat
|
heart.ap |
scr is a standard cells router, it makes an automatic placement and
routing of the heart.vst and gives the corresponding layout
description heart.ap .
|
heart.ap
|
druc_heart |
druc is a design rules checker, it looks for design in the layout
description heart.ap .
|
druc_heart heart.drc heart_drc.cif heart_rng.cif
|
heart.al | lynx of the heart. |
heart.al
|
lvx_heart | lvx of the heart. |
lvx_heart
|
chip.ap | ring routes the connections between the pads and the heart. | chip.ap |
druc_chip |
druc is a design rules checker, it looks for design in the layout
description chip.ap
|
druc_chip chip.drc chip_drc.cif chip_rng.cif
|
chip.al | lynx of the chip. |
chip.al
|
lvx_chip | lvx of the chip. |
lvx_chip
|
asimut_end | asimut of the chip. |
asimut_end res_pattern.pat
|
chip.vbe | yagle on the chip. |
chip.rep chip.vbe
|
proof_end |
proof between amd.vbe and chip.vbe .
|
proof_end
|
chip.ttv | tas on the chip. |
chip.rep chip.ttx
|
Am2901.cif | generates CIF description for 1.0 um process. |
am2901.cif
|
Once you have the heart.al
created, you can run graal to
see the layout:
> graal -l heart &
The same applies for chip.al
:
> graal -l chip &
Finally, once you have finished the tutorial, you can see the Am2901's layout
(am2901.cif
), using dreal:
> dreal -l am2901 &