Hi, On Thu, Apr 27, 2000 at 11:35:52PM +0200, Örjan Gustavsson wrote: > What am I doing wrong? > > I am trying to translate some very simple VHDL examples with > VASY/ASIMUT. So far none of my tests have worked, due to errors in the > vbe file generated by vasy. (At least asimut seems to think there is > errors :-) > > Since I am using the tools to learn VHDL, my confidence in my own code > is not that high. > > I'm attaching the original vhdl input to vasy, the generated vbe file > and the error messages from asimut. > > Regards, > Örjan Gustavsson > It's just because the output port q is in fact a register. Asimut doesn't accept output as registers. There are 2 solutions : 1) You introduce an intermediate signal 2) You take the last version of VASY, on the following URL: http://asim.lip6.fr/~ludo/vasy/ Regards, Ludo. (_) ___ Ludovic JACOMME _ _ ( ) ( ) ( ) ( 6 ) Laboratoire LIP6, Equipe ASIM ( ) (_) ( _ ) Couloir 55-65, 2eme etage, ( )___ ( ) Universite P. et M. Curie (P6) (_____) (_) 4 place Jussieu, 75252 Paris Cedex 05 Tel: (33) 01.44.27.54.15 Fax: (33) 01.44.27.72.80 ICQ: 62526530 mailto: Ludovic.Jacomme@asim.lip6.fr http: //asim.lip6.fr/~ludo