Hi there, Please could you tell me the reason for the errors I have encountered as I wanted to design a 3 bit counter from JK flipflops and 3 AND gates. Heres what I did: I used the vasy to get a (.vbe) description from a JK-flipflop vhdl description. Logical simulation of JK.vbe produced no errors. Next, I generated a test pattern and the behavioral simulation was ok. Mapping was done using boog, resulted in jk1.vst. I then created a structural (counter.vst) file describing the 3bit counter. Passing it through Asimut produced no syntax errors. I created my test pattern file (counter.pat) and this time upon simulation of the structural (counter.vst) description, I recieve errors such as: Error 111: illegal connections on signal `cout2` Error 111: illegal connections on signal `cout1` Error 111: illegal connections on signal `cout0` Using the figure below as guide, cout0 is the portion of (counter.vst) that the output of stage#1is fed in as the clock input of stage#2, cout1- output of stage#2 is fed in as clock-in of stage#3, cout2- output of stage#3 serves as the 3rd bit. Pls why do I get such "Illegal connection" errors. Thanks for your Help Giie. --------------------------------- Do You Yahoo!? Send your FREE holiday greetings online at Yahoo! Greetings.