Hi, Alliance VHDL subset is very particular (have a look on the manual pages vbe(5), vst(5), asimut) Asimut doesn't support process statement, so you have to use the prototype vasy in order to convert your VHDL description (with process statements) in Alliance VHDL subset (.vbe). For example for your description : (i've corrected all syntaxical mistakes) --- codegen.vhdl entity codegen is port( signal clk: in bit; signal din: in bit_vector(7 downto 0); signal dout: out bit_vector(7 downto 0); signal fout: out bit ); end codegen; architecture behavior of codegen is signal latch: bit_vector(7 downto 0); signal flipflop: bit; begin dout <= latch; fout <= flipflop; state: process(clk) begin if (clk'event and clk) then latch <= din; flipflop <= not flipflop; end if; end process state; end behavior; --- You have to run: > vasy -a -I vhdl codegen And vasy generates a file codegen_v.vbe : --- ENTITY codgen_v IS PORT( clk : IN BIT; din : IN BIT_VECTOR(7 DOWNTO 0); dout : OUT BIT_VECTOR(7 DOWNTO 0); fout : OUT BIT ); END codgen_v; ARCHITECTURE VBE OF codgen_v IS SIGNAL latch : REG_VECTOR(7 DOWNTO 0) REGISTER; SIGNAL flipflop : REG_BIT REGISTER; BEGIN LABEL0 : BLOCK ((clk = '1') AND NOT(clk'STABLE) ) BEGIN flipflop <= GUARDED '1'; END BLOCK LABEL0; LABEL1 : BLOCK ((clk = '1') AND NOT(clk'STABLE) ) BEGIN latch <= GUARDED din; END BLOCK LABEL1; fout <= flipflop; dout <= latch; END VBE; --- And the result file codgen_v.vbe can be simulated with Asimut. Have a look on man pages vasy(1) and vasy(5). Regards, Ludo. (_) ___ Ludovic JACOMME _ _ ( ) ( ) ( ) ( 6 ) Laboratoire LIP6, Equipe ASIM ( ) (_) ( _ ) Couloir 55-65, 2eme etage, ( )___ ( ) Universite P. et M. Curie (P6) (_____) (_) 4 place Jussieu, 75252 Paris Cedex 05 Tel: (33) 01.44.27.54.15 Fax: (33) 01.44.27.72.80 ICQ: 62526530 mailto: Ludovic.Jacomme@asim.lip6.fr http: //asim.lip6.fr/~ludo