alliance-support '02
Problem with addaccu and methodology


Vaclav Peroutka (vaclavp@s3group.cz)
Thu, 24 Jan 2002 19:34:23 +0100

Hello, yesterday I downloaded Alliance and started to play with it. I got version 4.0.6 from RPM archive for RedHat Linux. The first note is that some programs are looking for some crazy config files into /czo7 or something like that. The second note: I completely do not understand Alliance methodology. Why should I write any design twice ? I need to write VHDL, let's say I am good at it. Then I have to rewrite everything into C language (which I do not know) in order to run GENLIB ??? Why do you push engineers to do things twice ? Maybe it is not true, but in ADDACCU the only usage of addaccu.vbe was to simulate it. For the synthesis, only core.c is used. I can agree when I am setting pads etc. in C language, but not the whole design! The third note: Is it possible to compile larger design (in VHDL please), for example alu.vbe, cnt.vbe and ram.vbe entities are instantiated into main_file.vst ? I found an error when i tried to compile addaccu.vbe in fpgen. The design is really simple, so I do not know where is the problem. Let's have a look: 7:52:52 26> fpmap -TX4000 addaccu @@@@@@@@@ @@@ @@@ @@ @ @@ @@ @@ @ @@@ @@@ @@ @@@ @@@ @@@ @@@ @@@@ @@@ @@@ @@ @ @@@ @@ @ @@ @ @@ @@ @ @@@ @@ @@@@@@ @@ @@ @ @@ @ @@ @@ @@ @@ @@ @@ @ @@ @@ @ @@@ @@ @@@@@ @@ @@ @@ @@ @@ @ @@ @@ @@ @@ @@ @@ @@ @@ @@ @ @ @@ @@ @@ @@ @@ @@ @@@ @@ @ @@ @@ @@@ @@@ @@ @@@@@@ @@ @@@ @@@ @@@@ @@@@ @@ @@ @@@ @@ @@ @@@@ @@@@ Fpga Mapper Alliance CAD System 4.0.6, fpmap 1.01 Copyright (c) 1997-2002, ASIM/LIP6/UPMC E-mail support: alliance-support@asim.lip6.fr * FPGA environement: VHDL file : addaccu.vbe Expr file : addaccul.vbe Parameter file : none Architecture : X4000 Optimisation : -O2 Abl ordonancer : no Area / Delay : 40% area / 60% delay Iob mode : generate iobs Clocks : ck * MBK environement : MBK_IN_LO : vst MBK_OUT_LO : vst MBK_IN_PH : ap MBK_OUT_PH : ap MBK_WORK_LIB : . MBK_CATA_LIB : /usr/local/alliance/archi/Linux/cells/sc2sxlib/ * Loading vhdl file `addaccu.vbe' ... - Compiling ... fpmap: error: invalid block condition on register `reg 3' Is it possible to set fpmap somehow to have target technology for example Actel, Altera or others ? I will really appreciate if somebody can help me with some points here. Regards, Vaclav PS: addaccu.[pdf|ps] is quite out of date. It does not correspond with the attached Makefile at all. There is no "scr" library, in the doc is nothing about running dreal (or what is the name) and so on. -- Vaclav Peroutka IC Design Engineer Silicon & Software Systems Safrankova 1, Prague Email: vaclavp@s3group.cz

 



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