Table of Contents
rsa - Recurrence Solver Adder generator
rsa bits [ -cin ] [ -cout ] [ -overn ] [ -not ] [ -csa ] [ -sub ] [
-addsub ] [ -over ] [ -deci ] [ -stretch ] [ -stretch2 ] [ -msb0 ] [ -virtual
] [ -layout ] [ -icon ] [ -vhdl ] [ -patterns ] [ -datasheet ] [
-physicalbox ] [ -logicalbox ] [ -perf ] [ -o blockname ]
This software belongs to the ALLIANCE CAD system from the CAO-VLSI team at
ASIM/LIP6/UPMC laboratory.
LIP6/ASIM
University P. et M. Curie
4, place Jussieu
75252 PARIS Cedex 05
FRANCE
Fax : {33/0} 1.44.27.62.86
E-mail support : alliance-support@asim.lip6.fr
rsa is a fast adder generator for bit-sliced data-paths. The slice is
fixed to 60 lambdas, allows virtual terminals, and could be used with the
data-path compiler fitpath(1)
. The algorithm used is a binary carry-lookahead
adder (Recurrence Solver Adder) to offer the highest performance.
The technology employed is CMOS 5V nwell process.
Each signal name is predefined and can not be modified by the user. Each
signal name suffixed by _n indicates that the polarity signal is complemented.
Index 0 is the most significant bit when -msb0 is specified and
bits represent the number of bits. Signal names are :
- a[0]-a[bits-1] First input operand
-
- b[0]-b[bits-1] Second input operand
-
- c[0]-c[bits-1] Third input operand if option csa is selected.
-
- cin
- Carry in
- cout
- Last carry output
- coc
- Overflow when three operands
- co[0]-co[bits-1]
- Intermediates carries
- s[0]-s[bits-1] Sum result
-
- sub
- When is equal to 5V, it is a subtractor, otherwhise an
adder.
- vdd[],vss[]
- Power supplies
The width of the block is given by :
width = 73 + (27*(Log2(bits)+1)) + 67(if csa) + 16(if cout) lambdas
height = bits*60 lambdas
The generator needs a library cells to well compute. The MBK_CATA_LIB(1)
environment variable should contain the path to the library galib.
- bits
- The range is from 3 to 128 bits.
- -cin
- The generated adder will contain a carry input connector on the
North side in Metal1 layer.
- -cout
- The generated adder will contain all the intermediates carry,
accessible in Metal2 Layer, with the multi-access possibilities.
- -overn The generated adder will contain the previous carry output over
- in
Metal1 layer on the North side. This signal could be used to calculate
an overflow flag = over^cout.
- -not
- The output sum will be complemented but still keep the connector
name s.
- -csa
- The generated adder will be an adder with 3 operands, and one overflow
connector on the North side in Metal1 layer.
- -sub
- The adder generated is, in fact, a subtractor, and performs always
a-b. If the option -cin is present, then the block calculates
a+not(b)+cin .
- -addsub
-
The block obtained is a adder/subtractor. If the input terminal is
set to 5V then it is a subtractor. If the option -cin is present,
then the block performs a+xor(b,sub)+cin.
- -over -deci -stretch -stretch2
-
Bull Options.
- -msb0
- Default is index 0 for the least significant bit. When -msb0 is
present the the most significant bit is indexed with 0.
- -virtual
-
Default blocks contain fixed terminals. Virtual terminals can be
obtained using this option. This way, dpr(1)
routershouldoptimizedtheresultantrouteddata-path.
- -layout
-
The generated view asked is a layout view. The different formats
are given by mbk(1)
documentation, using MBK_OUT_PH(1)
environment
variable.
- -icon
- Icon view for schematic capture. The possible output formats are
specified setting the ICON_OUT (1) environement variable.
- -vhdl
- The generated view asked is a data-flow behavioural view. The
description of the VHDL used is gived by vhdl(5)
.
- -patterns
-
Some test vectors are proposed to validate the generated block. The
format used is the pat(5)
one accepted by the VHDL simulator
asimut(1)
.
- -datasheet
-
Principals process dependent informations are proposed to estimate
the adder performances. It is the default view if none is specified.
- -physicalbox
-
The generated view asked is a interface view. The different formats
are given by mbk(1)
documentation, using MBK_OUT_PH(1)
environment
variable.
- -logicalbox
-
The generated view asked is an interface netlist view. The different
formats are given by mbk(1)
documentation, using MBK_OUT_LO(1)
environment variable.
- -perf
- Programmer Option
- -oblockname
-
The generated adder name will be blockname.
rsa 32 -cin -cout -layout -vhdl
Produce the layout and vhdl view of a two operands adder with carry in and
final intermediates carries with the default name:
rsa32daaa.cp
rsa32daaa.vbe
- name.xx
- The layout and netlist views. The suffix depends on
the MBK_OUT_LO(1)
and MBK_OUT_PH(1)
environment variables.
name is blockname or, by default, prefixed by
rsa.
- name.vbe
- The VHDL behavioral view of the shifter.
- MBK_CATA_LIB
- contains the directory path of the recurrence solver
adder leaf cells library. This library is, by
default, in /labo/cells/rsa, and if not, depends upon
the system administrator installation.
- MBK_WORK_LIB
- contains the directory path of the working directory.
Usually set to . .
- MBK_IN_PH
- contains the format of the recurrence solver adder
leaf cells library.
- MBK_OUT_PH
- contains the desired format of the layout output.
- MBK_OUT_LO
- contains the desired format of the netlist output.
MBK_CATA_LIB(1)
, MBK_WORK_LIB(1)
, MBK_OUT_PH(1)
, MBK_OUT_LO(1)
,
MBK_IN_PH(1)
, vhdl(5)
, pat(5)
, fitpath(1)
, rfg(1)
, bsg(1)
, grog(1)
, genlib(1)
This tool is under development at the ASIM/LIP6/UPMC laboratory, cao-vlsi
research team.
We need your feedbak to improve documentation and tools.
If you find bugs, please fill-in the form at
http://asim.lip6.fr/alliance/support/bug-report/
Thanks for doing this.
Table of Contents
Alliance Web Site © 1997, 2002 ASIM/LIP6/UPMC,
page maintained by Czo [Olivier Sirol]
, last updated on 26 May 2000.