Dear Sir: Thanks for getting your software freely. I am planning the digital system design course, and trying the "alliance" tools for the course. The course covers from system design using VHDL to the implementation using FPGA, and focuses the front-end part. I am trying this procedure using the "alliance" software last week. Doing this, I have some questions: (1) The "vbe" manual wrotes that no sequential statement are supported. Most of VHDL-related materals use sequential statement (PROCESS). So we must change the VHDL code for simulation. Please let me know why sequential statements are missing. Also, I wonder if the "alliance" software supports "PROCESS" statement in the near future. (2) An error message in using "fpmap" : I am using "alliance" software, version 3.2b for Solaris under Solaris 2.5.1, and the version of X11 is X11R5. For FPGA mapping from .vbe to .xnf, the command below were run. % fpmap -TX4000 -af addaccu But .xnf file is not generated. The messages reported on the screen are: --------------------------------------------- (omitted) * Loading vhdl file `addaccu.vbe` ... - Compiling ... - Checking ... - Running the abl ordonancer ... authash.488 hash key 0 error ! --------------------------------------------- Please help us how to solve this problem. Thanks in advance. Regards, YunSeok Cho. ----------------------------------- School of Comp. Sci. & Elec. Eng. Handong University Pohang, Korea 791-940 ----------------------------------