I have written a small VHDL program called latchflop, which describes an 8-bit latch and a divide-by-2 flipflop. I type "asimut -c -b latchflop" and I get the following: initializing ... searching `latchflop` ... BEH : Compiling `latchflop.vbe` (Behaviour) ... `latchflop.vbe` Error line 19 : parse error `latchflop.vbe` Error 8 line 19 :bad architecture declaration BEH : Error 40: signal `flipflop` never assigned BEH : Error 40: signal `latch 0` never assigned BEH : Error 40: signal `latch 1` never assigned BEH : Error 40: signal `latch 2` never assigned BEH : Error 40: signal `latch 3` never assigned BEH : Error 40: signal `latch 4` never assigned BEH : Error 40: signal `latch 5` never assigned BEH : Error 40: signal `latch 6` never assigned BEH : Error 40: signal `latch 7` never assigned cannot continue further more. have a nice day... How do I fix this? phma
entity codegen is port( signal clk: in bit; signal din: in bit_vector(7 downto 0); signal dout: out bit_vector(7 downto 0); signal fout: out bit ); end codegen; architecture behavior of codegen is signal latch: bit_vector(7 downto 0); signal flipflop: bit; begin dout <= latch; fout <= flipflop; end state: process(clk); begin if (clk'event and clk) then latch <= din; flipflop <= not flipflop; end if; end process state; end behavior;