alliance-users '1998
Help-Standard Cells-


Luis A. Caceres (hakimus@univalle.edu.co)
Mon, 05 Oct 1998 12:20:39 -0500

--------------1FB6E5C4C4C45C307AAFB267 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit "In the way looking for the truth, the human stumble with it. At most times, he coming up, clean your clothes, and continue walking". Hello, good day for all. I need some urgent help .....I am stressed several days because I don't see any exit. Thanks (but very much thanks!!) in advance by your help. 1. I am using Alliance 3.2b. I am student working in your work grade. 2. I have problems with my custom cells. 3. I need documentation about VHDL from Alliance, the man pages and docs provided by Alliance not explain my doubts. * THIS IS MY WORK * THIS IS MY PROBLEM: * THIS IS THAT I NEED (I think): THIS IS MY WORK I am doing one circuit with some sub circuits, those with some standard cells and two (2) nonstandard cells. I am doing the structural description for interconnect this elements and sub circuits. After, I obtain the layout, the spice code, and go to simulation with Spice. As I need one non standard cell, (one C -Muller element), I have edited the layout (graal), later obtain the spice code (lynx), simulate, as all is ok Then I obtain the VHDL codes, netlists and more (lynx an yagle) and later put my C-muller cell as one Standard Cell in SClib (copying files and editing the CATAL file in /allaince/share/cells/sclib/). Later, I write the description structural in VHDL for one circuit that include my C-Muller cell. The system work good, with SCR I obtain my circuit, see the layout and all ok!!,...... [not all....in one case, the some metal 2 layers was "moved" 1 or 2 lambda's. I correct it editing the layout, and all ok.] With lynx I obtain the spice code, and all ok. I have described other cells, put it in the SCLIB, call in other VHDL structural description, obtain my layout, and more, and all ok. THIS IS MY PROBLEM I have described one circuit that include my C-muller cell. Obtain the layout, have simulate and all is ok. Call this circuit as "X" circuit. As I need this circuit (X) like one sub circuit for other circuit (say, circuit Y), I put the circuit X as one standard cell in the SCLIB. When I call the circuit X in some structural description, and trying to place a route the cells, with SCR, appear the problem: DON'T OBTAIN THE LAYOUT!!!!! The system, show the error : "the signal xyz is not defined (but isn't) or the abutment box is not present in the genlib library" Or, the system is trying to process for a while .....and never end. This problem is only with the circuit X. What have circuit X that no have the other circuits?? The circuit X have two outputs. I suspicious that this is the problem. THIS IS THAT I NEED First that all: I need more information/documentation/reference_manual about VHDL for Alliance. I have this questions: * Can the SCells have two o more outputs? * The complex of the circuits is growing. How can I to manipulate with VHDL structural mines custom cells, and sub circuits? Can I use configuration? Hoe define my architecture? There is other solution to my problem? (Well, the problem with the circuit X more than my ignorance with VHDL/Allaince) If anybody can help me, write soon!! Thanks very very much thanks in advance!!! ( Thanks * 10 exp n) Sincerely, and waiting for very much comments.... Luis A. Caceres Asynchronous VLSI design. hakimus@univalle.edu.co PD: Excuse me by my english. --------------1FB6E5C4C4C45C307AAFB267 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit

<HTML>

<CENTER><I>"In the way looking for the truth, the human&nbsp; stumble with
it.</I></CENTER>

<CENTER><I>At most times, he coming up, clean your clothes, and continue&nbsp;
walking".</I></CENTER>


<P>Hello, good day for all.

<P>I need some urgent help .....I am stressed several days because I don't
see any exit.
<BR>Thanks (but very much thanks!!) in advance by your help.

<P>1. I am using&nbsp; Alliance 3.2b. I am student working in your work
grade.
<BR>2. I have&nbsp; problems with my custom cells.
<BR>3. I need documentation about VHDL from Alliance, the man pages and
docs provided by
<BR>Alliance not explain my doubts.
<UL>
<LI>
&nbsp;<A HREF="#mywork">THIS IS MY WORK</A></LI>

<LI>
&nbsp;<A HREF="#myproblem">THIS IS MY PROBLEM:</A></LI>

<LI>
&nbsp;<A HREF="#ineed">THIS IS THAT I NEED (I think):</A></LI>
</UL>
<A NAME="mywork"></A>
<BR>THIS IS MY WORK
<BR>I am doing one circuit with some sub circuits, those with some standard
cells and two (2)
<BR>nonstandard cells. I am doing the structural description for interconnect
this elements
<BR>and sub circuits. After, I obtain the layout, the spice code, and go
to simulation with Spice.

<P>As I need one non standard cell, (one C -Muller element), I have edited
the layout (graal), later
<BR>obtain the spice code (lynx), simulate, as all is ok Then I obtain
the VHDL codes, netlists and more (lynx an yagle) and later put my C-muller
cell as one Standard Cell in SClib (copying files and editing&nbsp; the
CATAL file in /allaince/share/cells/sclib/).
<BR>Later, I write the description structural in VHDL for one circuit that
include my C-Muller cell.
<BR>The system work good, with SCR I obtain my circuit, see the layout
and all ok!!,......
<BR>[not all....in one case, the some metal 2 layers was "moved" 1 or 2
lambda's. I correct it editing the layout, and all ok.] With lynx I obtain
the spice code, and all ok.

<P>I have described other cells, put it in the SCLIB, call in other VHDL
structural description,
<BR>obtain my layout,&nbsp; and more, and all ok.
<BR><A NAME="myproblem"></A>
<BR>THIS IS MY PROBLEM
<BR>I have described one circuit that include my C-muller cell. Obtain
the layout, have simulate and all is ok. Call this circuit as "X" circuit.
<BR>As I need this circuit (X) like one sub circuit for other circuit (say,
circuit Y), I put the circuit X
<BR>as one standard cell in the SCLIB.
<BR>When I call the circuit X in some structural description, and trying
to place a route the cells, with
<BR>SCR, appear the problem:
<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
DON'T OBTAIN THE LAYOUT!!!!!
<BR>The system,&nbsp; show the error :
<BR><I>"the signal xyz is not defined (</I>but isn't<I>) or the abutment
box is</I>
<BR><I>not present in the genlib library"</I>
<BR>Or, the system is trying to process for a while .....and never end.

<P>This problem is only with the circuit X.
<BR>What have circuit X that no have the other circuits??
<BR>The circuit X have two outputs.
<BR>I suspicious that this is the problem.
<BR>&nbsp;
<BR><A NAME="ineed"></A>
<BR>THIS IS THAT I NEED

<P>First that all: I need more information/documentation/reference_manual
about VHDL for Alliance.
<BR>I have this questions:
<BR>&nbsp;
<UL>
<LI>
Can the SCells have two o more outputs?</LI>
</UL>

<UL>
<LI>
The complex of the circuits is growing. How can I to manipulate with VHDL
structural mines custom cells, and sub circuits?&nbsp; Can I use configuration?
Hoe define my architecture?</LI>
</UL>
There is other solution to my problem? (Well, the problem with the circuit
X more than my ignorance with VHDL/Allaince)

<P>If anybody can help me, write soon!!
<BR>Thanks very very much thanks in advance!!! ( Thanks * 10 exp n)

<P>Sincerely, and waiting for very much comments....

<P>Luis A. Caceres
<BR>Asynchronous VLSI design.
<BR>hakimus@univalle.edu.co

<P>PD: Excuse me by my english.</HTML>

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