-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v ISERDES_NODELAY.v -l ISERDES_NODELAY.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IOBUFDS_DIFF_OUT_INTERMDISABLE.v -l IOBUFDS_DIFF_OUT_INTERMDISABLE.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v MMCME4_ADV.v -l MMCME4_ADV.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v OBUFDS_DPHY.v -l OBUFDS_DPHY.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v ODDRE1.v -l ODDRE1.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IBUFDSE3.v -l IBUFDSE3.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v PLLE3_BASE.v -l PLLE3_BASE.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IBUFDS_INTERMDISABLE.v -l IBUFDS_INTERMDISABLE.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v DNA_PORTE2.v -l DNA_PORTE2.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v BITSLICE_CONTROL.v -l BITSLICE_CONTROL.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v XORCY.v -l XORCY.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v LDCE.v -l LDCE.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v CFGLUT5.v -l CFGLUT5.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v RX_BITSLICE.v -l RX_BITSLICE.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IBUFE3.v -l IBUFE3.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v OBUFDS_GTE4.v -l OBUFDS_GTE4.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v BUFG_GT.v -l BUFG_GT.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v RAMD32.v -l RAMD32.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v OUT_FIFO.v -l OUT_FIFO.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v SRL16E.v -l SRL16E.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v CMACE4.v -l CMACE4.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v GTHE2_CHANNEL.v -l GTHE2_CHANNEL.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IBUFDS_GTE4.v -l IBUFDS_GTE4.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v GTYE3_CHANNEL.v -l GTYE3_CHANNEL.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v OBUFDS_GTE4_ADV.v -l OBUFDS_GTE4_ADV.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v LUT3.v -l LUT3.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v DSP_PREADD.v -l DSP_PREADD.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v BUFHCE.v -l BUFHCE.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v ICAPE2.v -l ICAPE2.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IDDR_2CLK.v -l IDDR_2CLK.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v OBUFT.v -l OBUFT.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v RAM64X1S.v -l RAM64X1S.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IBUFDS_IBUFDISABLE_INT.v -l IBUFDS_IBUFDISABLE_INT.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v ISERDES.v -l ISERDES.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v GTHE3_COMMON.v -l GTHE3_COMMON.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v FIFO36E1.v -l FIFO36E1.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v LUT4.v -l LUT4.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v PHASER_OUT_PHY.v -l PHASER_OUT_PHY.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v RXTX_BITSLICE.v -l RXTX_BITSLICE.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IBUFCTRL.v -l IBUFCTRL.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v OBUF.v -l OBUF.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IOBUFDS.v -l IOBUFDS.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v OBUFDS_GTM_ADV.v -l OBUFDS_GTM_ADV.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v RAM256X1D.v -l RAM256X1D.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v HSDAC.v -l HSDAC.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v PCIE_2_1.v -l PCIE_2_1.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v GTXE2_COMMON.v -l GTXE2_COMMON.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v RAMB18E1.v -l RAMB18E1.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v USR_ACCESSE2.v -l USR_ACCESSE2.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v GTPE2_COMMON.v -l GTPE2_COMMON.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v LUT5.v -l LUT5.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v MASTER_JTAG.v -l MASTER_JTAG.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v SYSMONE4.v -l SYSMONE4.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v BUFG_GT_SYNC.v -l BUFG_GT_SYNC.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v PULLDOWN.v -l PULLDOWN.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v HSADC.v -l HSADC.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v PHASER_REF.v -l PHASER_REF.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IBUFDS_DIFF_OUT_IBUFDISABLE.v -l IBUFDS_DIFF_OUT_IBUFDISABLE.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v PHY_CONTROL.v -l PHY_CONTROL.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v SRLC32E.v -l SRLC32E.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v DSP_MULTIPLIER.v -l DSP_MULTIPLIER.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v BUFGCE.v -l BUFGCE.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v OSERDESE3.v -l OSERDESE3.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v XADC.v -l XADC.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v ICAPE3.v -l ICAPE3.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v CMAC.v -l CMAC.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v BUFIO.v -l BUFIO.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v URAM288_BASE.v -l URAM288_BASE.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v MUXF9.v -l MUXF9.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v GTHE4_CHANNEL.v -l GTHE4_CHANNEL.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v RAMS64E.v -l RAMS64E.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v PLLE2_ADV.v -l PLLE2_ADV.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IBUFDS_DPHY.v -l IBUFDS_DPHY.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v RAM512X1S.v -l RAM512X1S.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v TX_BITSLICE_TRI.v -l TX_BITSLICE_TRI.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v HARD_SYNC.v -l HARD_SYNC.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v RAM128X1D.v -l RAM128X1D.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v HBM_SNGLBLI_INTF_APB.v -l HBM_SNGLBLI_INTF_APB.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v FDSE.v -l FDSE.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v ZHOLD_DELAY.v -l ZHOLD_DELAY.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v PHASER_IN.v -l PHASER_IN.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v MMCME3_ADV.v -l MMCME3_ADV.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v BUFG.v -l BUFG.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v FIFO18E1.v -l FIFO18E1.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IBUF.v -l IBUF.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v OSERDESE2.v -l OSERDESE2.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IBUFDS_DIFF_OUT_INTERMDISABLE.v -l IBUFDS_DIFF_OUT_INTERMDISABLE.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IBUFDS_DIFF_OUT.v -l IBUFDS_DIFF_OUT.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IOBUF_ANALOG.v -l IOBUF_ANALOG.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v MMCME2_ADV.v -l MMCME2_ADV.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v RAM64M8.v -l RAM64M8.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v RAM32M.v -l RAM32M.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v LUT2.v -l LUT2.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v VCU.v -l VCU.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v DSP_ALU.v -l DSP_ALU.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v ODELAYE3.v -l ODELAYE3.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v GTXE2_CHANNEL.v -l GTXE2_CHANNEL.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v PLLE4_ADV.v -l PLLE4_ADV.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v SIM_CONFIGE2.v -l SIM_CONFIGE2.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v RFADC.v -l RFADC.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v PS8.v -l PS8.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v RAM256X1S.v -l RAM256X1S.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v BUFCE_LEAF.v -l BUFCE_LEAF.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v OBUFDS_GTE3_ADV.v -l OBUFDS_GTE3_ADV.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IOBUF_DCIEN.v -l IOBUF_DCIEN.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v DPHY_DIFFINBUF.v -l DPHY_DIFFINBUF.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v PS7.v -l PS7.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v PCIE4CE4.v -l PCIE4CE4.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v FIFO18E2.v -l FIFO18E2.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v FRAME_ECCE4.v -l FRAME_ECCE4.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v GTYE4_COMMON.v -l GTYE4_COMMON.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v HPIO_VREF.v -l HPIO_VREF.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v KEEPER.v -l KEEPER.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v RAM64M.v -l RAM64M.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v MUXCY.v -l MUXCY.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v BUFCE_ROW.v -l BUFCE_ROW.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v PCIE40E4.v -l PCIE40E4.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v BUFG_PS.v -l BUFG_PS.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v DSP_OUTPUT.v -l DSP_OUTPUT.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v BUFH.v -l BUFH.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IOBUFE3.v -l IOBUFE3.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v OR2L.v -l OR2L.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v PCIE_3_1.v -l PCIE_3_1.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IOBUFDS_DIFF_OUT.v -l IOBUFDS_DIFF_OUT.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v RAM32X1S.v -l RAM32X1S.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v STARTUPE2.v -l STARTUPE2.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v ISERDESE3.v -l ISERDESE3.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IOBUFDS_INTERMDISABLE.v -l IOBUFDS_INTERMDISABLE.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v GTPE2_CHANNEL.v -l GTPE2_CHANNEL.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v OBUFDS_GTM.v -l OBUFDS_GTM.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v RAM32X16DR8.v -l RAM32X16DR8.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v PHASER_OUT.v -l PHASER_OUT.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v DCM_ADV.v -l DCM_ADV.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v OSERDESE1.v -l OSERDESE1.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v SIM_CONFIGE3.v -l SIM_CONFIGE3.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v LUT1.v -l LUT1.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v RAMS64E1.v -l RAMS64E1.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v FDCE.v -l FDCE.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v RAMS32.v -l RAMS32.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v INV.v -l INV.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IOBUFDS_DCIEN.v -l IOBUFDS_DCIEN.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v OBUFDS_GTE3.v -l OBUFDS_GTE3.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v MMCME4_BASE.v -l MMCME4_BASE.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v LDPE.v -l LDPE.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v DSP_PREADD_DATA.v -l DSP_PREADD_DATA.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v DNA_PORT.v -l DNA_PORT.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IBUFDS.v -l IBUFDS.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v FRAME_ECCE3.v -l FRAME_ECCE3.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v HBM_TWO_STACK_INTF.v -l HBM_TWO_STACK_INTF.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v DIFFINBUF.v -l DIFFINBUF.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v FE.v -l FE.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v ODELAYE2_FINEDELAY.v -l ODELAYE2_FINEDELAY.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IBUFDS_IBUFDISABLE.v -l IBUFDS_IBUFDISABLE.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v PLLE4_BASE.v -l PLLE4_BASE.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v BUFGP.v -l BUFGP.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v GTYE3_COMMON.v -l GTYE3_COMMON.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v ILKNE4.v -l ILKNE4.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v CAPTUREE2.v -l CAPTUREE2.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v PCIE_3_0.v -l PCIE_3_0.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v SYSMONE1.v -l SYSMONE1.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v GTHE2_COMMON.v -l GTHE2_COMMON.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IDDRE1.v -l IDDRE1.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v RAM64X1D.v -l RAM64X1D.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v MUXF8.v -l MUXF8.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v DSP_C_DATA.v -l DSP_C_DATA.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v RAMD64E.v -l RAMD64E.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v RAM32X1D.v -l RAM32X1D.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v STARTUPE3.v -l STARTUPE3.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v VCC.v -l VCC.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v BUFR.v -l BUFR.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v LUT6.v -l LUT6.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IOBUFDSE3.v -l IOBUFDSE3.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IBUF_INTERMDISABLE.v -l IBUF_INTERMDISABLE.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v AUTOBUF.v -l AUTOBUF.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v HBM_SNGLBLI_INTF_AXI.v -l HBM_SNGLBLI_INTF_AXI.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IN_FIFO.v -l IN_FIFO.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v ODELAYE2.v -l ODELAYE2.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v DSP48E2.v -l DSP48E2.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v RAM128X1S.v -l RAM128X1S.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v MMCME2_BASE.v -l MMCME2_BASE.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v SRLC16E.v -l SRLC16E.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v DSP_A_B_DATA.v -l DSP_A_B_DATA.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v DSP_M_DATA.v -l DSP_M_DATA.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v OBUFTDS.v -l OBUFTDS.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v FDRE.v -l FDRE.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v BSCANE2.v -l BSCANE2.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v PLLE2_BASE.v -l PLLE2_BASE.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v PULLUP.v -l PULLUP.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v PLLE3_ADV.v -l PLLE3_ADV.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v GTYE4_CHANNEL.v -l GTYE4_CHANNEL.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v ODDR.v -l ODDR.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v DCIRESET.v -l DCIRESET.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v OSERDES.v -l OSERDES.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v GTHE3_CHANNEL.v -l GTHE3_CHANNEL.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v GND.v -l GND.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v OBUFT_DCIEN.v -l OBUFT_DCIEN.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v PHASER_IN_PHY.v -l PHASER_IN_PHY.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v JTAG_SIME2.v -l JTAG_SIME2.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IBUFDS_GTE2.v -l IBUFDS_GTE2.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v OBUFTDS_DCIEN.v -l OBUFTDS_DCIEN.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IBUFDS_GTE3.v -l IBUFDS_GTE3.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IDELAYE2.v -l IDELAYE2.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IOBUFDS_DIFF_OUT_DCIEN.v -l IOBUFDS_DIFF_OUT_DCIEN.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v RAM32M16.v -l RAM32M16.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v EFUSE_USR.v -l EFUSE_USR.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v CARRY8.v -l CARRY8.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v RIU_OR.v -l RIU_OR.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v DSP48E1.v -l DSP48E1.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IOBUF_INTERMDISABLE.v -l IOBUF_INTERMDISABLE.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v RAMB18E2.v -l RAMB18E2.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v FRAME_ECCE2.v -l FRAME_ECCE2.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IBUFDS_INTERMDISABLE_INT.v -l IBUFDS_INTERMDISABLE_INT.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v RAMB36E2.v -l RAMB36E2.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v RAMB36E1.v -l RAMB36E1.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v ISERDESE1.v -l ISERDESE1.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v BUF.v -l BUF.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v HBM_REF_CLK.v -l HBM_REF_CLK.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v DCM_SP.v -l DCM_SP.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v RAMD32M64.v -l RAMD32M64.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v FIFO36E2.v -l FIFO36E2.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v URAM288.v -l URAM288.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v HBM_ONE_STACK_INTF.v -l HBM_ONE_STACK_INTF.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v AND2B1L.v -l AND2B1L.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v OBUFDS.v -l OBUFDS.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v FDPE.v -l FDPE.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v CARRY4.v -l CARRY4.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v LUT6_2.v -l LUT6_2.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v BIBUF.v -l BIBUF.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v MUXF7.v -l MUXF7.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v BUFGCE_DIV.v -l BUFGCE_DIV.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IBUF_ANALOG.v -l IBUF_ANALOG.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v RFDAC.v -l RFDAC.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v BUFGCTRL.v -l BUFGCTRL.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IBUFDS_GTM.v -l IBUFDS_GTM.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IBUF_IBUFDISABLE.v -l IBUF_IBUFDISABLE.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v MMCME3_BASE.v -l MMCME3_BASE.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v BUFMRCE.v -l BUFMRCE.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IOBUF.v -l IOBUF.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v INBUF.v -l INBUF.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v GTHE4_COMMON.v -l GTHE4_COMMON.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IDELAYCTRL.v -l IDELAYCTRL.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IDDR.v -l IDDR.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v RAM64X8SW.v -l RAM64X8SW.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IDELAYE3.v -l IDELAYE3.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v BUFMR.v -l BUFMR.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v TX_BITSLICE.v -l TX_BITSLICE.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v IDELAYE2_FINEDELAY.v -l IDELAYE2_FINEDELAY.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v ISERDESE2.v -l ISERDESE2.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v ILKN.v -l ILKN.v.log
-cd verilog/src/unisims -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns ../glbl.v GTM_DUAL.sv -l GTM_DUAL.sv.log