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Subsections

7.6 Other Processors


7.6.1 MCS51 variants

MCS51 processors are available from many vendors and come in many different flavours. While they might differ considerably in respect to Special Function Registers the core MCS51 is usually not modified or is kept compatible.

pdata access by SFR

With the upcome of devices with internal xdata and flash memory devices using port P2 as dedicated I/O port is becoming more popular. Switching the high byte for pdata access which was formerly done by port P2 is then achieved by a Special Function Register. In well-established MCS51 tradition the address of this sfr is where the chip designers decided to put it. As pdata addressing is used in the startup code for the initialization of xdata variables a separate startup code should be used as described in section 3.12.

Other Features available by SFR

Some MCS51 variants offer features like Double DPTR, multiple DPTR, decrementing DPTR, 16x16 Multiply. These are currently not used for the MCS51 port. If you absolutely need them you can fall back to inline assembly or submit a patch to SDCC.

7.6.2 The Z80 and gbz80 port

SDCC can target both the Zilog and the Nintendo Gameboy's Z80-like gbz80. The Z80 port is passed through the same regressions tests as MCS51 and DS390 ports, so floating point support, support for long variables and bitfield support is fine.

As always, the code is the authoritative reference - see z80/ralloc.c and z80/gen.c. The stack frame is similar to that generated by the IAR Z80 compiler. IX is used as the base pointer, HL is used as a temporary register, and BC and DE are available for holding variables. IY is currently unused. Return values are stored in HL. One bad side effect of using IX as the base pointer is that a functions stack frame is limited to 127 bytes - this will be fixed in a later version.


next up previous contents index
Next: 7.7 Retargetting for other Up: 7 SDCC Technical Data Previous: 7.5 Cyclomatic Complexity   Contents   Index
Bernhard Held 2003-08-29