![[ICO]](/icons/blank.gif){kind=icon}
![[PARENTDIR]](/icons/back.gif){kind=icon}
![[DIR]](/icons/folder.gif){kind=icon}
![[ ]](/icons/unknown.gif){kind=icon}
![[ ]](/icons/p.gif){kind=icon}
![[TXT]](/icons/text.gif){kind=icon}
| Name | Last modified | Size | Description |
|---|---|---|---|---|
| Parent Directory | - | ||
| APPNOTE_011_Design_Investigation/ | 2023-08-05 11:14 | - | |
| CHAPTER_Approach.rst | 2023-08-05 11:14 | 5.2K | |
| CHAPTER_Basics.rst | 2023-08-05 11:14 | 32K | |
| CHAPTER_CellLib.rst | 2023-09-23 16:29 | 41K | |
| CHAPTER_Eval.rst | 2023-08-05 11:14 | 11K | |
| CHAPTER_Intro.rst | 2023-08-05 11:14 | 4.6K | |
| CHAPTER_Memorymap.rst | 2023-08-05 11:14 | 19K | |
| CHAPTER_Optimize.rst | 2023-08-05 11:14 | 12K | |
| CHAPTER_Overview.rst | 2023-08-05 11:14 | 25K | |
| CHAPTER_Prog.rst | 2023-08-05 11:14 | 1.3K | |
| CHAPTER_Prog/ | 2023-08-05 11:14 | - | |
| CHAPTER_Techmap.rst | 2023-08-05 11:14 | 5.0K | |
| CHAPTER_Verilog.rst | 2023-08-05 11:14 | 26K | |
| appendix/ | 2023-08-05 11:14 | - | |
| bib.rst | 2023-08-05 11:14 | 124 | |
| cmd_ref.rst | 2023-08-05 11:14 | 271 | |
| conf.py | 2023-08-05 11:14 | 1.4K | |
| index.rst | 2023-08-05 11:14 | 2.1K | |
| literature.bib | 2023-08-05 11:14 | 7.6K | |
| requirements.txt | 2023-08-05 11:14 | 40 | |