1  `define ST_STOP  3'b001
      2  `define ST_GO    3'b010
      3  `define ST_SLOW  3'b100
      4  
      5  module main;
      6  
      7  reg        clk;
      8  reg        go;
      9  wire [2:0] state;
     10  
     11  fsma fsm1( clk, go, state );
     12  fsmb fsm2( clk, go );
     13  
     14  wire error = (state[0] & state[1]) || (state[0] & state[2]) || (state[1] & state[2]) || (state == 3'b000);
     15  
     16  initial begin
     17  	$dumpfile( "example.vcd" );
     18  	$dumpvars( 0, main );
     19  	go = 1'b0;
     20  	repeat( 10 ) @(posedge clk);
     21  	go = 1'b1;
     22  	#10;
     23  	$finish;
     24  end
     25  
     26  initial begin
     27  	clk = 1'b0;
     28  	forever #(1) clk = ~clk;
     29  end
     30  
     31  endmodule
     32  
     33  module fsma( clk, go, state );
     34  
     35  input        clk;
     36  input        go;
     37  output [2:0] state;
     38  
     39  reg [2:0] next_state;
     40  reg [2:0] state;
     41  
     42  initial begin
     43  	state = `ST_SLOW;
     44  end
     45  
     46  always @(posedge clk) state <= next_state;
     47  
     48  (* covered_fsm, lights, is="state", os="next_state" *)
     49  always @(state or go)
     50    case( state )
     51      `ST_STOP :  next_state = go ? `ST_GO : `ST_STOP;
     52      `ST_GO   :  next_state = go ? `ST_GO : `ST_SLOW;
     53      `ST_SLOW :  next_state = `ST_STOP;
     54    endcase
     55  
     56  assert_one_hot #(.width(3)) zzz_check_state ( clk, 1'b1, state );
     57  
     58  endmodule
     59  
     60  module fsmb( clk, go );
     61  
     62  input     clk;
     63  input     go;
     64  
     65  reg [2:0] next_state;
     66  reg [2:0] state;
     67  
     68  initial begin
     69          state = `ST_STOP;
     70  end
     71  
     72  always @(posedge clk) state <= next_state;
     73  
     74  (* covered_fsm, lights, is="state", os="next_state",
     75                          trans="3'b001->3'b010",
     76                          trans="3'b010->3'b100",
     77                          trans="3'b100->3'b001" *)
     78  always @(state or go)
     79    case( state )
     80      `ST_STOP :  next_state = go ? `ST_GO : `ST_STOP;
     81      `ST_GO   :  next_state = go ? `ST_GO : `ST_SLOW;
     82      `ST_SLOW :  next_state = `ST_STOP;
     83    endcase
     84  
     85  assert_one_hot #(.width(3)) zzz_check_state ( clk, 1'b1, state );
     86  
     87  endmodule