# packages

pkgId: 3d47dae137d83daa1bcf985d63f8b7f6c70b40fcae73dc87bc1dccc804ee052f
name: alliance
arch: src
version: 5.0
epoch: 0
release: 111.1
summary: VLSI EDA System
url: http://coriolis.lip6.fr/
rpm_license: GPL-2.0-only
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Applications/Engineering
rpm_buildhost: i03-ch2d
location_href: src/alliance-5.0-111.1.src.rpm
checksum_type: sha256
description:
  Alliance is a complete set of free CAD tools and portable libraries for
  VLSI design. It includes a VHDL compiler and simulator, logic synthesis
  tools, and automatic place and route tools.

  A complete set of portable CMOS libraries is provided, including a RAM
  generator, a ROM generator and a data-path compiler.

  Alliance is the result of more than ten years effort spent at ASIM department
  of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France).

  Alliance has been used for research projects such as the 875 000 transistors
  StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL
  Router.

  You are kindly requested to mention
  " Designed with alliance (c) LIP6, Sorbonne Université"
  so as to spread the word about "alliance CAD system" and its development team.

  Alliance provides CAD tools covering most of all the digital design flow:

   * VHDL Compilation and Simulation
   * Model checking and formal proof
   * RTL and Logic synthesis
   * Data-Path compilation
   * Macro-cells generation
   * Place and route
   * Layout edition
   * Netlist extraction and verification
   * Design rules checking


pkgId: 4b47f4943758e56f9b6c8650c24831ec8ed0b232a0a73d8c1a15c16f96776872
name: coriolis-eda
arch: src
version: 2.5.5
epoch: 0
release: 223.1.744e2daed
summary: Coriolis 2 EDA toolchain
url: https://coriolis.lip6.fr/
rpm_license: BSD-1-Clause AND LGPL-2.0-only AND GPL-2.0-only AND Apache-1.0
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Applications/Engineering
rpm_buildhost: i03-armsrv2
rpm_packager: Mazher Iqbal <mazher@lip6.fr>
location_href: src/coriolis-eda-2.5.5-223.1.744e2daed.src.rpm
checksum_type: sha256
description:
  A FOSS EDA tool suite for physical design. Provides an integrated
  place & route for ASICs. Support symbolic layout (Alliance) and
  real layout (GDS). While mainly written in C++, it has an extensive
  Python interface.


pkgId: d3aca65f2c44b3fc59bb22fd0be8bd1c31d3ca800e637804f159037484a04607
name: coriolis-pdk-gf180mcu
arch: src
version: 2025.07.21
epoch: 0
release: 5.1.bfa7190
summary: Global Foundries 180 MCU open PDK
url: https://github.com/google/gf180mcu-pdk.git
rpm_license: Apache-2.0
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Unspecified
rpm_buildhost: h02-ch2d
location_href: src/coriolis-pdk-gf180mcu-2025.07.21-5.1.bfa7190.src.rpm
checksum_type: sha256
description:
  The GF180MCU  open source PDK  is a collaboration between  Google and
  GlobalFoundries to  provide a  fully open  source process  design kit
  (PDK)  and  related  resources  to enable  the  creation  of  designs
  manufacturable at GlobalFoundries's facility  on their 0.18um 3.3V/6V
  MCU process technology.

  The GF180MCU documentation can be found at <https://gf180mcu-pdk.rtfd.io>.


pkgId: d5ee706571d9a30712bca4227e4ed6d0a9688ad299ebba28009beaa5ace310f0
name: coriolis-pdk-ihpsg13g2
arch: src
version: 2025.07.21
epoch: 0
release: 11.1.bfa7190
summary: IHP Open PDK SG13G2
url: https://github.com/IHP-GmbH/IHP-Open-PDK
rpm_license: Apache-2.0
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Unspecified
rpm_buildhost: i03-ch2c
location_href: src/coriolis-pdk-ihpsg13g2-2025.07.21-11.1.bfa7190.src.rpm
checksum_type: sha256
description:
  130nm  BiCMOS Open  Source PDK,  dedicated for  Analog/Digital, Mixed
  Signal and RF Design

  IHP Open  Source PDK project  goal is to  provide a fully  open source
  Process  Design Kit  and related  data, which  can be  used to  create
  manufacturable  designs at  IHP’s facility.   As of  March 2023,  this
  repository is targeting the SG13G2 process node


pkgId: 22dd82852f055c347c38ec17c6ea050b657cb8e8be5b49fd78d79dc840711ef5
name: ngspice
arch: src
version: 44.2
epoch: 0
release: 7.1
summary: Mixed-level, Mixed-signal Circuit Simulator Based on spice3f5
url: https://ngspice.sourceforge.io
rpm_license: BSD-2-Clause
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Productivity/Scientific/Electronics
rpm_buildhost: h02-ch1c
location_href: src/ngspice-44.2-7.1.src.rpm
checksum_type: sha256
description:
  Ngspice is a mixed-level/mixed-signal circuit simulator. Its code
  is based on three open source software packages: Spice3f5, Cider1b1
  and Xspice.


pkgId: b331d42310f17309727bb1534d7a1e5631509d00986945594bf45a09948bfa0b
name: openvaf
arch: src
version: 23.5.0
epoch: 0
release: 5.1
summary: OpenVAF is a Next-Generation Verilog-A compiler
url: https://openvaf.semimod.de/
rpm_license: GPL-3.0-only
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Applications/Engineering
rpm_buildhost: i02-ch2c
location_href: src/openvaf-23.5.0-5.1.src.rpm
checksum_type: sha256
description:
  Circuit simulators play a critical role in the design of electrical circuits.
  Accurate simulations enable circuit designers to validate circuit behavior
  before actual fabrication happens, potentially saving significant re-design
  costs.  The simulation of a circuit critically depends on the so-called compact
  models and therefore:
  * The accuracy of the compact-model equations
  * The quality of the model parameters


pkgId: 03c9672f2bb23eb8d465988ce6cb9c27bca26ca26f6f540ef761222ce26b67bb
name: sv2v
arch: src
version: 0.0.12
epoch: 0
release: 1.1
summary: sv2v - SystemVerilog to Verilog
url: https://github.com/zachjs/sv2v/
rpm_license: BSD-3-Clause
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Applications/Engineering
rpm_buildhost: i04-ch4c
location_href: src/sv2v-0.0.12-1.1.src.rpm
checksum_type: sha256
description:
  sv2v converts SystemVerilog (IEEE 1800-2017) to Verilog (IEEE 1364-2005),
  with an emphasis on supporting synthesizable language constructs.
    The primary goal of this project is to create a completely free and
  open-source tool for converting SystemVerilog to Verilog. While methods
  for performing this conversion already exist, they generally either rely
  on commercial tools, or are limited in scope.
    This project was originally developed to target Yosys, and so allows for
  disabling the conversion of (passing through) those SystemVerilog features
  that Yosys supports.


pkgId: 89a901a6204edd5a1c480726ea34f784246117d8dc4a0da8a450151d345d9c58
name: tas-yagle
arch: src
version: 3.4.6
epoch: 0
release: 169.1.fa4d642
summary: Tas/Yagle - Static Timing Analyser
url: https://coriolis.lip6.fr/
rpm_license: GPL-2.0-only
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Applications/Engineering
rpm_buildhost: i02-ch2a
location_href: src/tas-yagle-3.4.6-169.1.fa4d642.src.rpm
checksum_type: sha256
description:
  STATIC TIMING ANALYSIS
    The  advent   of  semiconductor  fabrication  technologies   now  allows  high
  performance in complex integrated circuits.
    With the increasing complexity of these circuits, static timing analysis (STA)
  has  revealed  itself  as  the  only  feasible  method  ensuring  that  expected
  performances are actually obtained.
    In addition, signal integrity (SI) issues due to crosstalk play a crucial role
  in performance and reliability of these  systems, and must be taken into account
  during the timing analysis.
    However, performance  achievement not  only lies in  fabrication technologies,
  but also  in the way circuits  are designed.  Very high  performance designs are
  obtained with semi or full-custom designs techniques.
    The HITAS platform provides advanced STA and SI solutions at transistor level.
  It has been  built-up in order to allow engineers to  ensure complete timing and
  SI coverage on their digital custom  designs, as well as IP-reuse through timing
  abstraction.
    Furthermore,  hierarchy  handling  through  transparent  timing  views  allows
  full-chip verification, with virtually no limit of capacity in design size.


pkgId: 50c7468169ac635eefb0f9c59df3d057c7bd9548510ed57014c117a7bcedb208
name: temurin-8-jdk
arch: src
version: 8.0.472.0.0.8
epoch: 0
release: 10.1
summary: Eclipse Temurin 8 JDK
url: https://projects.eclipse.org/projects/adoptium
rpm_license: GPLv2 with exceptions
rpm_vendor: Eclipse Adoptium
rpm_group: java
rpm_buildhost: i03-ch1a
rpm_packager: Eclipse Adoptium Package Maintainers <temurin-dev@eclipse.org>
location_href: src/temurin-8-jdk-8.0.472.0.0.8-10.1.src.rpm
checksum_type: sha256
description:
  Eclipse Temurin JDK is an OpenJDK-based development environment to create
  applications and components using the programming language Java.


pkgId: de73484d49a96c1497c525f8f2436a2326eff1a152fe26a11fc9a089e672ad33
name: texlive-picinpar
arch: src
version: 2014
epoch: 0
release: 1.1
summary: Insert pictures into paragraphs.
rpm_license: GPL+
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Unspecified
rpm_buildhost: i03-ch1b
location_href: src/texlive-picinpar-2014-1.1.src.rpm
checksum_type: sha256
description:
  A legacy package for creating 'windows' in paragraphs, for
  inserting graphics, etc. (including "dropped capitals"). Users
  should note that Piet van Oostrum (in a published review of
  packages of this sort) does not recommend this package; Picins
  is recommended instead.

  CTAN Catalogue Date: 2012-06-13 09:18:45 +0200


pkgId: 14951584d4e6118dd063a3c4bcac1cfb82ecc58ee6b34e048803debb0eeedcbb
name: yosys
arch: src
version: 0.58
epoch: 0
release: 11.1.157aabb58
summary: Yosys open synthesis suite
url: https://yosyshq.net/yosys/
rpm_license: ISC
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Applications/Engineering
rpm_buildhost: i04-ch2d
location_href: src/yosys-0.58-11.1.157aabb58.src.rpm
checksum_type: sha256
description:
  This is a framework for RTL synthesis tools. It currently has
  extensive Verilog-2005 support and provides a basic set of
  synthesis algorithms for various application domains.

  Yosys can be adapted to perform any synthesis job by combining
  the existing passes (algorithms) using synthesis scripts and
  adding additional passes as needed by extending the yosys C++
  code base.

  Yosys is free software licensed under the ISC license (a GPL
  compatible license that is similar in terms to the MIT license
  or the 2-clause BSD license).


pkgId: 4311d26b3775f47f2c737b96039d65d4d7a25ecef7c2fb208e896cdc14122045
name: yosys-slang
arch: src
version: 2025.10.31.ba1859e
epoch: 0
release: 19.1
summary: SystemVerilog frontend for Yosys
url: https://github.com/povik/yosys-slang.git
rpm_license: ISC
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Applications/Engineering
rpm_buildhost: i01-ch2a
location_href: src/yosys-slang-2025.10.31.ba1859e-19.1.src.rpm
checksum_type: sha256
description:
  yosys-slang is  a Yosys plugin  providing a new  command (read_slang)
  for loading SystemVerilog designs.
    yosys-slang  builds   on  top  of  the  slang  library  to  provide
  comprehensive   SystemVerilog  support.   The   plugin  supports   an
  (informally defined) synthesizable subset of SystemVerilog in version
  IEEE 1800-2017 or IEEE 1800-2023.


