yosys - Yosys open synthesis suite
| License: | GPL |
|---|
- Description:
Yosys is a synthesis suite for FPGAs and ASICs. It includes a verilog parser and the logic synthetizer ABC.
Packages
| yosys-0.9.git1926013-1.el7.soc.x86_64 [10.5 MiB] |
Changelog
by Jean-Paul Chaput (2020-02-17):
- Update to version 0.9 and ABC 3709744. |
| yosys-0.9.git049e3abf9baf795e69b9ecb9c4f19de6131f8418-1.el7.soc.x86_64 [10.5 MiB] |
Changelog
by Jean-Paul Chaput (2020-02-17):
- Update to version 0.9 and ABC 3709744. |
| yosys-0.9.git3209c07-1.el7.soc.x86_64 [10.5 MiB] |
Changelog
by Jean-Paul Chaput (2020-02-17):
- Update to version 0.9 and ABC 3709744. |
| yosys-0.9-1.el7.soc.x86_64 [7.2 MiB] |
Changelog
by Jean-Paul Chaput (2020-02-17):
- Update to version 0.9 and ABC 3709744. |
| yosys-0.7-1.el7.soc.x86_64 [5.9 MiB] |
Changelog
by Jean-Paul Chaput (2018-03-21):
- Update to version 0.7 and ABC to 77d52065fd97. |
| yosys-0.5-2.el7.soc.x86_64 [4.8 MiB] |
Changelog
by Gabriel.Gouvine (2015-04-06):
- Packaged the 0.5 version of yosys - Do not download ABC through the net but use an archive. |