yosys - Yosys open synthesis suite

License: GPL
Yosys is a synthesis suite for FPGAs and ASICs.
It includes a verilog parser and the logic synthetizer ABC.


yosys-0.7-1.el7.soc.x86_64 [5.9 MiB] Changelog by Jean-Paul Chaput (2018-03-21):
- Update to version 0.7 and ABC to 77d52065fd97.
yosys-0.5-2.el7.soc.x86_64 [4.8 MiB] Changelog by Gabriel.Gouvine (2015-04-06):
- Packaged the 0.5 version of yosys
- Do not download ABC through the net but use an archive.

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